February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY March 05, 1:30pm - 3:00pm | Oak Ballroom
EVENT TYPE: PANEL
Did We Create the Verification Gap?
Moderator:
John Blyler - Extension Media
Organizer:
JL Gray - Cadence Design Systems, Inc.
According to industry experts, the “Verification Gap” between what we need to do and what we’re actually able to do to verify large designs is growing worse each year. According to these experts, we must do our best to improve our verification methods and tools before our entire project schedule is taken up by verification tasks.

But what if the Verification Gap is actually occurring as a result of continued adoption of industry standard methods. Are we blindly following industry best practices without keeping in mind that the actual point of our efforts is to create a product with as few bugs as possible, as opposed to simply trying to find as many bugs as we can?

Panelists will explore how verification teams interact with broader project teams and examine the characteristics of a typical verification effort, including the wall between design and verification, verification involvement (or lack thereof) in the design and architecture phase, and reliance on constrained random in absence of robust planning and prioritization to determine the reasons behind today’s Verification Gap.


Panelists:
Janick Bergeron - Synopsys, Inc.
Jim Caravella - NXP Semiconductors
Harry Foster - Mentor, A Siemens Business
John Goodenough - Arm, Ltd.
Bill Grundmann - Xilinx Inc.
Mike Stellfox - Cadence Design Systems, Inc.