MONDAY March 03, 2:00pm - 5:00pm | San Martin/San Simeon Room
Henrik Svensson - Ericsson
Christian Sauer - Cadence Design Systems, Inc.
Martin Barnasconi - NXP Semiconductors
Donald Cramb - Synopsys, Inc.
John Stickley - Mentor, A Siemens Business
For more than a decade, SystemC has been used by system architects and design engineers. In more recent times Transaction Level Modeling (TLM2) and virtual prototyping have been an integral part of rewriting some of the models and enhancing the design and verification methodologies from earlier efforts. They have continued to deploy evolving methodologies in new application areas such as radio base station and network processors to bring-up software months ahead of the traditional approach. Other users have attempted to bridge the interoperability gap between SystemC and Universal Verification Methodology (UVM) based on SystemVerilog and other HDLs. In this tutorial, hands-on users and tool developers share their recent experience and describe advanced methodologies that have helped them achieve significant benefits. A few of the most useful features introduced with SystemC 2.3.0 will be presented and provide code examples that you can take away and start to use for yourself.