February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY February 29, 9:00am - 12:00pm | Oak
TOPIC AREA: SYSTEMVERILOG FOR VERIFICATION AND/OR DESIGN
EVENT TYPE: TUTORIAL

SESSION 1T
Preparing for IEEE UVM Plus UVM Tips and Tricks

Speakers:
Doug Perry - Doulos Ltd.
Srivatsa Vasudevan - Synopsys, Inc.
Organizer:
Adam Sherer - Accellera Systems Initiative
UVM is poised to make the great leap to the IEEE with the work in the 1800.2 committee. In preparation for this new step and as part of the work done in the iEEE, there are changes you should know about the IEEE version of the standard. Some of the most significant changes are involve retiring hidden APIs. Knowing what these are can help you prepare for the new standard. This part of the tutorial will provide code examples and recommendations from experts working in the IEEE.

While we are preparing for the future, we do need to get chips out now. Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. There are also a number of common errors, that are hard to recognize because the compiler gets off on the wrong track early, and never recovers. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This part of the tutorial will walk through an introduction of UVM testbench features, a working examples including common errors and fixes, and conclude with the built in debugging features in UVM and how to use them.