February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY March 02, 8:30am - 9:30am | Oak/Fir
EVENT TYPE: PANEL
Redefining ESL
Moderator:
Brian Bailey - Semiconductor Engineering
Organizers:
Dave Kelf - OneSpin Solutions GmbH
Nanette Collins - Nanette V. Collins Marketing and Public Relations
Brian Bailey of Semiconductor Engineering recently wrote an article titled, “What ESL Is Really About.” ESL is not a design flow, he noted, it is a verification flow, and it will not take off until the industry recognizes that. With as many views as there are fragmented pieces of ESL, panelists will have plenty of angles to consider as they discuss raising the abstraction from the register transfer level (RTL) for both design and verification. For example, HLS raises design abstraction, but only works well for certain parts of the design. Portable stimulus raises the abstraction of test specification. Formal works at this level because assertions can be written similarly to parts of the specification. It is a fragmented mess –– different inputs to the main design effort the starts at RTL –– that will be a lively debate.

DVCon attendees are invited to join Brian and a panel of distinguished experts who will attempt to define ESL verification, from tools to flows. They will attempt to answer: How or when can all the disparate pieces be brought together, or is that even necessary?

Panelists:
Adnan Hamid - Breker Verification Systems, Inc.
Dave Pursley - Cadence Design Systems, Inc.
Bryan Bowyer - Mentor, A Siemens Business
Simon Davidmann - Imperas Software Ltd.
Raik Brinkmann - OneSpin Solutions GmbH
Patrick Sheridan - Synopsys, Inc.