MP Associates, Inc.

TUESDAY March 01, 9:00am - 10:30am | Fir
EVENT TYPE: REGULAR SESSION

SESSION 2
Design and Modeling Approaches
Chair:
Stuart Sutherland - Sutherland HDL, Inc.

2.1Full Flow Clock Domain Crossing - From Source to Si
 Speaker: Mark Litterick - Verilab Ltd.
 Author: Mark Litterick - Verilab Ltd.
2.2Modeling Analog Systems Using Full Digital Simulations, a State Space Approach
 Speaker: Rajat K. Mitra - Cadence Design Systems, Inc.
 Author: Rajat K. Mitra - Cadence Design Systems, Inc.
2.3Applying High-Level Synthesis for Synthesizing Hardware Runtime STL Monitors of Mission-Critical Properties
 Speaker: Konstantin Selyunin - Vienna Univ. of Technology
 Authors: Konstantin Selyunin - Vienna Univ. of Technology
Thang Nguyen - Infineon Technologies AG
Andrei-Daniel Basa - Infineon Technologies AG
Ezio Bartocci - Vienna Univ. of Technology
Dejan Nickovic - Institute of Science and Technology Austria
Radu Grosu - Vienna Univ. of Technology