March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY February 29, 2:00pm - 5:00pm | Oak

Cut Your Design Time in Half with Higher Abstraction

Bob Condon - Intel Corp.
Frederic Doucet - Qualcomm Technologies, Inc.
Peter Frey - Mentor, A Siemens Business
Mike Meredith - Cadence Design Systems, Inc.
Dirk Seynhaeve - Intel Corp.
Adam Sherer - Accellera Systems Initiative
In the quarter century that RTL has been our main digital design abstraction, the silicon devices that we build have grown 4 orders of magnitude in gate count. Our projects are managing millions of lines of code eating into our design and verification efficiency. Such dizzying growth makes the design engineer wonder — is it time to move up abstraction again?

We in the Accellera SystemC Synthesis Working Group (SSWG) think the answer is YES. The most recent draft of a synthesizable subset standard for SystemC has been available for public review and we’d like to introduce it to you. This tutorial is focused on the engineer today who is coding in Verilog/SystemVerilog or VHDL. We will explain how to use the language subset to write synthesizable models at a higher level of abstraction than RTL. We will provide real code examples comparing algorithms written at RTL and those written using the synthesizable subset, explaining the reasons behind the coding choices and the downstream implications for RTL and gates. We will also discuss how a synthesis standard is the foundation for a full design and verification ecosystem at a higher level of abstraction and the value that can bring to the designer.

We’ll conclude with some potential directions for the synthesis subset that will further enable the HLS ecosystem and a Q/A panel session with our presenters.