February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY February 29, 2:00pm - 5:00pm | Fir
KEYWORD: MIXED-SIGNAL MODELING AND VERIFICATION
EVENT TYPE: TUTORIAL

SESSION 4T
SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling

Speakers:
Martin Vlach - Mentor, A Siemens Business
Scott Little - Intel Corp.
Organizer:
Scott Little - Intel Corp.
In the 2012 revision of SystemVerilog, nettypes and interconnect were added to provide language features for modeling analog/mixed-signal (AMS) circuits. While these constructs are useful, they do not provide a complete solution for those interested in complex AMS modeling scenarios. Verilog-AMS is a much more complete AMS modeling solution, but it is based on the Verilog IEEE Std 1364-2005 standard which has been superseded by SystemVerilog.

Over the past two years, a small group of Verilog-AMS and SystemVerilog experts have been meeting with the goal of unifying SystemVerilog and Verilog-AMS. This tutorial will provide an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard.