MP Associates, Inc.

THURSDAY March 03, 8:30am - 12:00pm | Donner
KEYWORD: LOW-POWER DESIGN AND VERIFICATION TECHNIQUES
EVENT TYPE: TUTORIAL

SESSION 5T
Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips

Speakers:
Gabriel Chidolue - Mentor, A Siemens Business
Shantanu Samant - Mentor, A Siemens Business
Jonathan Lovett - Mentor, A Siemens Business
Organizer:
Rebecca Granquist - Mentor, A Siemens Business
Driven by process technology needs, government legislation, and continued product integration and miniaturization, reducing power consumption is a mainstream primary design requirement for many industry segments; including networking, mobile, consumer, and IoT markets. More designs now employ sophisticated power management techniques.

For example, design teams implement more power domains per design with each power domain placed in many different power states that balances power consumption with system performance requirements, leading to an exponential growth in power domain interactions that must be thoroughly verified. Since overall system power management is usually handled in software, software interactions with hardware power management logic must be verified. Furthermore, designers need to ensure that the entire system stays within its power budget as it traverses its legal power state space. Finally, it is imperative that power management strategies and their verification begin as early as possible in order to facilitate and maximize power saving opportunities at the architectural level.

In this tutorial, you will learn the latest advances in power architecture specification, leveraging existing UPF standards and emerging low-power design methodologies—such as “Successive Refinement” UPF methodology. You will also learn how new constructs in IEEE p1801 – 2015 aka UPF 3.0 can facilitate power modeling at high levels of abstraction and improve application of “Successive Refinement” methodology. Mentor Graphics, industry experts, and customers will discuss new trends in the use of EDA tools for the functional verification of power managed designs.

The following will also be discussed in this tutorial:
* Application of Static Power aware checking techniques
* Power-aware simulation for early verification of the logical power management architecture captured in the constraints and configuration UPFs as well as the technology specific implementation UPF necessary for implementation tools. Specifically, we will explore coverage closure and debug adapted for power aware simulations.
*Leveraging emulation technology for verification of power management logic interactions with system software and for estimation of system power consumption under realistic software loads
*Introduction to system-level power modeling at the SystemC level of abstraction.


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