February 26 - March 1, 2018

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY February 27, 9:00am - 12:00pm | Oak
TOPIC AREA: PORTABLE STIMULUS
EVENT TYPE: TUTORIAL

SESSION 1T
Creating Portable Stimulus Models with the Upcoming Accellera Standard

Speakers:
David Brownell - Analog Devices, Inc.
Sharon Rosenberg - Cadence Design Systems, Inc.
Tom Fitzpatrick - Mentor, A Siemens Business
Adnan Hamid - Breker Verification Systems, Inc.
Srivatsa Vasudevan - Synopsys, Inc.
Faris Khundakjie - Intel Corp.
Sandeep Pendharkar - Vayavya Labs Pvt., Ltd.
Organizer:
Barbara Benjamin - Accellera Systems Initiative

Portability of reusable test cases has long been a goal for semiconductor verification and validation teams. No one wants to “reinvent the wheel” by having to rewrite similar tests again and again. While the widely accepted, Accellera Universal Verification Methodology (UVM) standard, enabled reuse of testbench components and constrained-random tests at the IP and block level, limitations in terms of reuse at subsystem and full-chip level, and lack of portability across execution platforms required a fresh look at addressing the portable stimulus and test challenge. Accellera Systems Initiative formed the Portable Stimulus Working Group (PSWG) in early 2015 to do just that. The group’s charter is to define a portable test and stimulus standard specification to permit the creation of a single representation/model, usable by a variety of users across different levels of integration under different configurations, enabling the generation of different implementations that run on a variety of execution platforms, including, but not limited to, simulation, emulation, FPGA prototyping, and post-silicon. With such a specification in place, EDA vendors can produce tools that automatically generate stimulus, results checks, and coverage metrics tuned for a particular target. The first version of the Accellera Portable Test and Stimulus Standard (PSS) is nearing completion. This timely tutorial presents an introduction to the standard’s main features leveraging a series of usage examples defined by PSWG members that represent many of the common challenges faced in today’s multi-core designs. The tutorial will show with actual coding examples how the verification and portability challenges of these examples are met using the standard.

Attendees will learn how to:

• Understand and develop abstract, portable test and stimulus models for their chip designs

• Use PSS constraints to guide randomization of both data and control flow to describe a legal scenario space to be verified

• Target use of existing low-level sequences or drivers in the generation of tests

• Execute generated tests across platforms from simulation, emulation, FPGA prototype, and post-silicon to verify a complete chip or multi-chip system

• Specify and gather coverage metrics at every step to assess verification completeness


Sponsored by: