February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
MONDAY February 27, 2:00pm - 5:00pm | Fir
TOPIC AREA: SYSTEMC /C/C++ DESIGN AND/OR VERIFICATION OF SYSTEMS
EVENT TYPE: TUTORIAL
SESSION 3T
SystemC Design and Verification – Solidifying the Abstraction Above RTL

Speakers:
Trevor Wieman - Intel Corp.
Peter Frey - Mentor, A Siemens Business
Karsten Einwich - COSEDA Technologies
Martin Barnasconi - NXP Semiconductors
Organizer:
Ellie Burns - Accellera Systems Initiative
Each year the EDA community makes critical advances in SystemC.    As we do, the momentum toward SystemC as the primary point of entry above RTL becomes more tantalizing.  Will this be the year your team makes the leap?  This tutorial could answer that question for you.
 
We will focus on three key components that could help you make that decision: design, modeling, and testbench.  We’ll start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration.  A discussion of modeling for high-performance simulation will follow to complete our view of the overall design.  Of course, we need to verify this fast-running design with a testbench approach that can be reused at RTL so we’ll discuss how to apply the emerging UVM-SystemC standard.  We’ll complete the tutorial with a Q/A session with all of our presenters focusing on the remaining work they see to help you make the leap to the SystemC abstraction.

Sponsored by: