February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
TUESDAY February 28, 12:00pm - 1:15pm | Pine/Cedar
EVENT TYPE: SPONSORED LUNCHEON
SESSION 31
Application Specific Verification from Edge Nodes through Hubs, Networks and Servers – Are the Requirements all the Same?
Moderator:
Ed Sperling - Semiconductor Engineering
Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc.
With the “Internet of Things” (IoT) connecting billions of “things”, all of them aggregating data through hubs and sending them through networks to cloud servers for big data analytics across different application domains, how does that change verification of the different components involved? Do the same flows and development requirements apply to designs that enable the cloud, networks, hubs and edge nodes? With the IoT spanning across a variety of application domains, how do those requirements play into verification? After an introduction of the different application domains and how they relate to the IoT, the panel will discuss application specific aspects for verification of the different designs at the IP, Sub-system, Chip and System-level. Are the key drivers different? Is power optimization more critical in some designs than it is in others? Are the design cycles forcing early software development and different forms of prototyping in some application areas more than in others? Are safety critical design flows as important in IoT edge nodes as in automotive?

Panelists:
James Hogan - Vista Ventures
Christopher Lawless - Intel Corp.
David Lacey - Hewlett Packard Enterprise
Frank Schirrmeister - Cadence Design Systems, Inc.
Frank Schirrmeister
Senior Group Director
Cadence Design Systems

Frank Schirrmeister is Senior Group Director, Product Management, System Development, System & Verification Group (SVG) at Cadence. He drives product management of the Cadence System Development Suite with a focus on hardware engines and software enablement, accelerating system integration, validation, and bring-up with a set of connected platforms for concurrent HW/SW design and verification. Frank holds a MSEE from the Technical University of Berlin.

Christopher C. Lawless
Director, External Customer Acceleration
Intel Corporation

Chris Lawless is Director, External Customer Acceleration in Intel’s Software and Services Group’s System Technologies and Optimization Division. He leads and is responsible for delivering customer facing pre-silicon strategies to advance the IA ecosystem and accelerate customer time-to-market Lawless joined Intel in 1995 and has held a variety of positions including Director of the Pre-Silicon Platforms Acceleration Division in the Platform Engineering Group, where he led prototyping solutions to enhance Intel’s pre-silicon capabilities and to shift left, Director of Strategic Investments with Intel Capital, managing the Security Investment Practice and invested in deals across multiple sectors, Manager of Strategic Technology for Intel’s Internet Media Services, Senior Product Manager for Business Communications Products Operation (Intel ProShare® Videoconferencing), among others. Before rejoining Intel in 2010, Lawless was Senior Vice President, Corporate Development and Marketing with Signacert, a tier-one venture backed company (Acquired by Harris Corp), and served as Managing Director for Hunterwise Securities, a global investment bank where he focused on the technology sector. Lawless is the co-inventor of five technology patents. He graduated from the University of Maryland where he received his Bachelors of Science degree in Business Administration.

David Lacey
Verification Scientist
Hewlett Packard Enterprise

David Lacey received his Master's Degree in Electrical Engineering from Louisiana Tech University and has been working in system design for 27 years. His experience spans across embedded systems specification and design, hardware design, and FPGA and ASIC design and verification. For the last 17 years, he has been Hewlett Packard Enterprise where, as a Verification Scientist, he helps shape verification methodologies. His lab develops ASIC chips for use in a variety of HPE products, including the HPE Superdome class of supercomputers and HPE’s Proliant servers. He is part of the engineering team that is developing technologies that are driving a new class of memory-driven computing that makes up The Machine.

James Hogan
Vista Ventures

Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 40 years gaining experience as a senior executive and board director in electronic design automation, intellectual property, semiconductor equipment, material science and IT companies.




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