March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY February 28, 1:30pm - 2:30pm | Oak/Fir
The Right Tool (or Tools) for the Toughest Verification Tasks
Jean-Marie Brunet - Mentor, A Siemens Business
Nanette Collins - Nanette V. Collins Marketing and Public Relations
Emulation, simulation, formal verification and FPGA prototyping, along with a mix of methodologies, are often evaluated by verification groups to assess their ability to solve every conceivable verification challenge. Some verification groups tout emulation as the primary verification technology as simulation reaches its outer limits and FPGA prototyping is consigned to smaller designs. They now consider emulation to be among the most capable tools to meet their challenging chip design verification requirement through better reliability, more use models and greater flexibility. Of course, the verification checkerboard benefits from the adoption of formal verification as it too has more use models and a significant number of expert users. Accellera’s Portable Stimulus standard could play some role in the future, predicts a handful of verification engineers. New developments on the verification front promise to fuel a fascinating discussion among panelists who will describe how decisions are made about which tools are implemented in a design verification flow. And how budgets are allocated. As users, they will explain why some tools dominate today’s flow and others not so much.

Nasr Ullah - Samsung Austin R&D Center
Bill Neifert - Arm, Ltd.
Alex Starr - Advanced Micro Devices, Inc.
Guy Hutchison - Cavium
Suman K. Mandal - Intel Corp.