THURSDAY March 01, 10:30am - 12:00pm | Sierra
KEYWORD: FORMAL METHODOLOGY AND STATIC ANALYSIS
EVENT TYPE: SHORT WORKSHOP
Jonathan Bromley - Verilab, Inc.
Jason Sprott - Verilab, Inc.
Building on our well-received foundation-level tutorial Formal Verification – Too Good to Miss presented at DVCon Europe 2016, this session will cover some of the more advanced techniques and workflow patterns that have proven valuable in our own formal verification work. Carefully avoiding mathematical jargon, it aims to demystify some approaches that help to make a formal verification project productive. Black-boxing, using abstractions for counters and other common structures, and exploiting design symmetry are often mentioned, but rarely described in an accessible way. They will all be covered in a practical style, emphasising broad applicability. In addition to purely technical content, the session will illustrate how to approach the planning and tracking of your formal verification project – concerns that are easily overlooked in the initial enthusiasm of adopting formal. This tutorial is appropriate for engineers who are embarking on, or part-way through, a project that uses formal verification. It tackles troublesome questions that commonly become challenges for anyone as their experience deepens: how to establish metrics and criteria for project progress, knowing when you’re done, overcoming performance and capacity issues, achieving confidence in the robustness and trustworthiness of your formal verification environment, and integrating results from formal into your simulation-based verification flow.
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