MP Associates, Inc.

MONDAY February 26, 2:00pm - 5:00pm | Oak/Fir
KEYWORD: SYSTEMVERILOG FOR VERIFICATION AND/OR DESIGN
EVENT TYPE: TUTORIAL

SESSION 2T
IEEE-Compatible UVM Reference Implementation and Verification Components

Speakers:
Justin Refice - NVIDIA Corp.
Mark Strickland - Cisco Systems, Inc.
Uwe Simm - Cadence Design Systems, Inc.
Mark Peryer - Mentor, A Siemens Business
Srivatsa Vasudevan - Synopsys, Inc.
Organizer:
Justin Refice - NVIDIA Corp.
On April 11, 2017, the IEEE Standards Association (IEEE-SA) approved the IEEE 1800.2™ Standard for Universal Verification Methodology (UVM). For the tens of thousands of UVM verification engineers, this milestone connects teams to a standard recognized worldwide. However, the milestone does come with change. On one hand, there are many improvements and new features in the IEEE standard. On the other hand, there are changes to the both the standardized and undocumented APIs that many engineers accessed in the Accellera reference implementation to build their verification components.
 
This tutorial will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM WG. The speakers will use the new reference implementation to describe the new features and changes relative to UVM 1.2. Engineers attending the tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples and interactive discussions with members of the Accellera UVM WG will help engineers gain the practical knowledge they need to adopt the IEEE 1800.2™ Standard for UVM.
 

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