March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY February 27, 10:30am - 12:00pm | Gateway Foyer
EVENT TYPE: POSTER SESSION

SESSION 4
Poster Session
Chair:
Srivatsa Vasudevan - Synopsys, Inc.

4.1Creating the Optimal Regression Farm Infrastructure That Meets All Your Team’s Simulation Requirements
 Speaker: David Lacey - Hewlett Packard Enterprise
 Authors: David Lacey - Hewlett Packard Enterprise
Ed Powell - Hewlett Packard Enterprise
4.2Rockin' the Polymorphism for an Elegant UVM Testbench Architecture for a Scalable, Highly Configurable, Extensible DUT
 Speaker: Michael Baird - Willamette HDL
 Authors: Michael Baird - Willamette HDL
Frank Verhoorn - Northwest Logic Inc.
4.3UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling
 Speaker: Ahmed M. Ahmed Kamal - Mentor, A Siemens Business
 Author: Ahmed M. Ahmed Kamal - Mentor, A Siemens Business
4.4Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify your use Model
 Speaker: Thomas Ellis - Mentor, A Siemens Business
 Authors: Thomas Ellis - Mentor, A Siemens Business
Rohit Jain - Mentor, A Siemens Business
4.5Verification Strategy for Pipeline Type of Design
 Speaker: Djuro P. Grubor - VTool Ltd.
 Author: Djuro P. Grubor - VTool Ltd.
4.6Sub-Design Interface Aware Top Only Low Power Verification
 Speaker: Heichang Lee - Synopsys, Inc. & Samsung Electronics Co., Ltd.
 Authors: Heichang Lee - Synopsys, Inc. & Samsung Electronics Co., Ltd.
Nikhil Amin - Synopsys India Pvt. Ltd.
Jianfeng Liu - Samsung Electronics Co., Ltd.
Minyoung Mo - Samsung Electronics Co., Ltd.
Dongkwan Han - Samsung Electronics Co., Ltd.
4.7A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic
 Speaker: Kurt Takara - Mentor, A Siemens Business
 Authors: Priya Viswanathan - Mentor, A Siemens Business
Kurt Takara - Mentor, A Siemens Business
Chris Kwok - Mentor, A Siemens Business
Islam Ahmed - Mentor, A Siemens Business
4.8Context-Aware DFM Rule Analysis and Scoring Using Machine Learning
 Speaker: Vikas Tripathi - GLOBALFOUNDRIES
 Authors: Vikas Tripathi - GLOBALFOUNDRIES
Yongfu Li - GLOBALFOUNDRIES
I-Lun Tseng - GLOBALFOUNDRIES
Valerio Perez - GLOBALFOUNDRIES
Jonathan Ong - GLOBALFOUNDRIES
Zhao Chuan Lee - GLOBALFOUNDRIES
4.9Proper Probing: Flexibility on the TLM level
 Speaker: Gergo Vekony - AImotive
 Author: Gergo Vekony - AImotive
4.10Holistic Approach to IO Timing Verification Using Portable Stimulus and Assertions
 Speaker: Amitesh Khandelwal - Infineon Technologies AG
 Authors: Amitesh Khandelwal - Infineon Technologies AG
Praveen Kumar - Infineon Technologies AG
4.11Managing and Automating Hw/Sw Tests from IP to SoC
 Speaker: Matthew Ballance - Mentor, A Siemens Business
 Author: Matthew Ballance - Mentor, A Siemens Business
4.12Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis
 Speaker: Sulabh K. Khare - Mentor, A Siemens Business
 Authors: Jackie Hsiung - MediaTek, Inc.
Ashish Hari - Mentor, A Siemens Business
Sulabh K. Khare - Mentor, A Siemens Business
4.13An Analytical View of Test Results Using Cityscapes
 Speaker: Daniel Hansson - Verifyter AB
 Authors: Markus Borg - SICS Swedish ICT
Andreas Brytting - KTH Royal Institute of Technology
Daniel Hansson - Verifyter AB
4.14Reusable UPF : Transitioning from RTL to Gate Level Verification
 Speaker: Durgesh Prasad - Mentor, A Siemens Business
 Authors: Durgesh Prasad - Mentor, A Siemens Business
Jitesh Bansal - Mentor, A Siemens Business & Accenture
Madhur Bhargava - Mentor, A Siemens Business
4.15Hybrid Approach to Testbench and Software Driven Verification on Emulation
 Speaker: Debdutta Bhattacharya - Mentor, A Siemens Business
 Authors: Debdutta Bhattacharya - Mentor, A Siemens Business
Ayub Khan - Mentor, A Siemens Business
4.16Fast Track Formal Verification Signoff
 Speaker: Mandar Munishwar - Qualcomm Technologies, Inc.
 Authors: Mandar Munishwar - Qualcomm Technologies, Inc.
Xiaolin Chen - Synopsys, Inc.
Arunava Saha - Synopsys, Inc.
Sandeep Jana - Synopsys India Pvt. Ltd.
4.17What Time Is It: Implementing a SystemVerilog Object-Oriented Wrapper for Interacting with the C Library time
 Speaker: Eldon G. Nelson - Synopsys, Inc.
 Author: Eldon G. Nelson - Synopsys, Inc.
4.18Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages
 Speaker: Timothy Pertuit - Hewlett Packard Enterprise
 Authors: Timothy Pertuit - Hewlett Packard Enterprise
Doug Gibson - Hewlett Packard Enterprise
David Lacey - Hewlett Packard Enterprise
4.19Formal Verification of Silicon for Software Defined Networking
 Speaker: Saurabh Shrivastava - Cavium
 Authors: Saurabh Shrivastava - Cavium
Anh Tran - Cavium & Xpliant, Inc.
Keqin Han - Cavium
Chirag Agarwal - Oski Technology, Inc.
Ankit Saxena - Oski Technology, Inc.
Anshul Jain - Oski Technology, Inc.
Achin Mittal - Oski Technology, Inc.
Roger Sabbagh - Oski Technology, Inc.
4.20SoC Verification of Analog IP Integration through Automated, Formal-based, Rule-driven Spec Generation
 Speaker: Murugesh Palaniswamy - Synaptics Incorporated
 Authors: Murugesh Palaniswamy - Synaptics Incorporated
Ravi Kalyanaraman - Synaptics Incorporated
Gargi Sharma - Mentor, A Siemens Business
Bharat Baliga-Savel - Mentor, A Siemens Business
4.21Rapid VLSI Design Process-Hotspot Detection Using Machine Learning
 Speaker: Robert Pack - GLOBALFOUNDRIES
 Authors: Piyush Verma - GLOBALFOUNDRIES
Robert Pack - GLOBALFOUNDRIES
Robert E. Boone - GLOBALFOUNDRIES
Karthik Krishnamoorthy - GLOBALFOUNDRIES
Fadi Batarseh - GLOBALFOUNDRIES
Sriram Madhavan - GLOBALFOUNDRIES
4.22UVM Testbench Design for ISA Functional Verification of a Microprocessor
 Speaker: Gabriel Wang - MediaTek, Inc.
 Authors: Gabriel Wang - MediaTek, Inc.
Hongtao Ma - MediaTek, Inc.
Maoduo Sun - MediaTek, Inc.
4.23SGEN2: Evolution of a Sequence-Based Stimulus Engine for Micro-Processor Verification
 Speaker: Stephan Bourduas - Cavium
 Authors: Stephan Bourduas - Cavium
Christopher Mikulis - Cavium
4.24Synthesis of Decoder Tables Using Formal Verification Tools
 Speaker: Keerthikumara Devarajegowda - Infineon Technologies AG & Technische Univ. Kaiserslautern
 Authors: Keerthikumara Devarajegowda - Infineon Technologies AG & Technische Univ. Kaiserslautern
Johannes Schreiner - Infineon Technologies AG & Technische Univ. München
Wolfgang Ecker - Infineon Technologies AG & Technische Univ. München
4.25Ultimate Shift Left: Unleash the Power of UVM Virtual LAB Methodology Upon SOC Verification
 Speaker: Roman Wang - Advanced Micro Devices, Inc.
 Author: Roman Wang - Advanced Micro Devices, Inc.
4.26Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology
 Speakers: Gabriel Chidolue - Mentor, A Siemens Business
Rohit Jain - Mentor, A Siemens Business
 Authors: Rohit Jain - Mentor, A Siemens Business
Shobana Sudhakar - Mentor, A Siemens Business
4.27Making Security Verification "SECURE"
 Speaker: Nagesh N. Ranganath - Analog Devices, Inc.
 Authors: Subin Thykkoottathil - Analog Devices, Inc.
Nagesh N. Ranganath - Analog Devices, Inc.
4.28Don’t Delay Catching Bugs: Using UVM Based Architecture to Model External Board Delays
 Speaker: Vikas Makhija - Synopsys India Pvt. Ltd.
 Authors: Amit Paunikar - Synopsys India Pvt. Ltd.
Saurabh Arya - Synopsys India Pvt. Ltd.
Vikas Makhija - Synopsys India Pvt. Ltd.
Shaily Khare - Synopsys India Pvt. Ltd.
4.29Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Model
 Speaker: Anwesha Choudhury - Mentor, A Siemens Business
 Authors: Anwesha Choudhury - Mentor, A Siemens Business
Ashish Hari - Mentor, A Siemens Business
4.30Cleaning Out Your Pipes - Pipeline Debug in UVM Testbenches
 Speaker: Rich Edelman - Mentor, A Siemens Business
 Authors: Rich Edelman - Mentor, A Siemens Business
Neil Bulman - Arm, Ltd.
4.31Improving Verification Predictability and Efficiency Using Big Data
 Speaker: Darron K. May - Mentor, A Siemens Business
 Author: Darron K. May - Mentor, A Siemens Business