February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
MONDAY February 25, 1:45pm - 3:15pm | Oak
SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC

Mike Meredith - Cadence Design Systems, Inc.
Dragos Dospinescu - AMIQ
Fred Doucet - Facebook
Bob Condon - Intel Corp.
Dragos Dospinescu - AMIQ
Mark Glasser - NVIDIA Corp.

This Short Workshop on SystemC will provide an overview on High Level Synthesis (HLS) with a discussion on data types and model structure as well as lessons learned.  The presentation on HLS will be followed by a 30 minute tutorial on Functional Coverage for SystemC.  We’ll close the workshop with an update on the Accellera SystemC Working Group, with an opportunity for attendees to ask questions from the presenters.
High-Level Synthesis with SystemC: An Introduction 
Speaker: Frederic Doucet, Facebook

Writing a hardware design in SystemC model and using High-level Synthesis (HLS) to synthesize it to a register transfer level (RTL) model can yield many significant productivity benefits when compared to traditional RTL design flows. In this talk, we describe the fundamental structures of a SystemC design model, and what is abstracted in a SystemC model that is explicit in an RTL model. We then show how HLS tools are be used to concretize the abstraction into the desired structures in the RTL model, the productivity benefits and the remaining challenges in typical HLS flows. 
High Level Synthesis: Model Structure and Data Types
Speaker: Mike Meredith, Cadence Design Systems, Inc.

SystemC models used as input for synthesis must be properly structured. They differ in important ways from models used for virtual platform development and other purposes. Differences include restrictions in the C++ and SystemC constructs that can be used and a much greater use of SystemC bit-accurate datatypes and fixed-point datatypes.  The issues surrounding model structure and data types for synthesis will be discussed in this session.
High Level Synthesis: Lessons Learned
Speaker: Bob Condon, Intel Corp.

SystemC HLS usage has matured and product teams have used it for multiple generations of designs.   We present some lessons learned in wide-scale deployment.   We will cover some techniques for triaging HLS errors, how HLS fits in power flows, and techniques repurposed from the software engineering world to make code easier to maintain over multiple generations.
Functional Coverage for SystemC (FC4SC)
Speaker: Dragos Dospinescu, AMIQ

Functional coverage lies at the core of functional verification as the primary metric that assesses the quality of the entire verification process. This notion of functional coverage can be extended from the scope of RTL verification to the verification of any type of application.
The Functional Coverage for SystemC (FC4SC) is a header-only library that provides mechanisms for functional coverage definition, collection and reporting that can be used in any application which is compliant with the C++ standard, starting with C++11.
In this presentation, we will give you an introduction into FC4SC's capabilities, accompanied by examples of how to use the library for constructing and managing your coverage model. FC4SC use cases primarily involve (but are not limited to) measuring the level of exercise of SystemC models in order to track the features that are tested. This includes anything ranging from block level functional coverage, up to system level scenarios.  Reference: https://github.com/amiq-consulting/fc4sc
Accellera SystemC Working Group update
Speaker: Mike Meredith, Cadence Design Systems, Inc.

A number of activities are currently underway within the Accellera Technical Working Groups that are of interest to the SystemC community.  Working groups involved in SystemC standardization cover the SystemC Language, SystemC Synthesis, SystemC Verification, SystemC Analog/Mixed Signal and SystemC Configuration, Control and Inspection.  A brief update on the activities of these working groups will be given.


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