March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY February 27, 3:00pm - 4:30pm | Oak
EVENT TYPE: REGULAR SESSION

SESSION 11
Power-Aware Design and Verification
Chair:
Progyna Khondkar - Mentor, A Siemens Business
Power-aware verification in a variety of applications.

11.1Supply Network Connectivity: An Imperative Part in Low Power Gate-level Verification
Gate level simulation is an important step in verification of low power behavior. Simulation corruption semantics applied when verifying such designs often depend on power related attributes defined in the liberty views of the cells or in case of complex Macro cells on the Verilog Power Aware model itself. Both are a function of the supply pin states of the cells. Ensuring that the power supply network is complete and accurate is therefore absolutely fundamental for a successful simulation of such netlists. This paper proposes a methodology for automatic supply network connections in the presence of incomplete UPF supply specification
 Speaker: Progyna Khondkar - Mentor, A Siemens Business
 Authors: Divyeshkumar D. Vora - Arm, Ltd.
Vinay K. Singh - Mentor Graphics (India) Pvt. Ltd.
Progyna Khondkar - Mentor, A Siemens Business
11.2UVM and UPF: An Application of UPF Information Model
Due to ever increasing complexity of today’s SoC designs, sophisticated verification methodologies like UVM have gained popularity. However, more designs now use power management strategies to minimize power consumption, written in the UPF specification as a side file. There hasn’t been a proper integration of UVM with the UPF standard – leading to adhoc or proprietary extensions. In this paper, we will provide an application of the UPF Information Model APIs to enable UVM interact with low power designs having UPF. This will address the problem of UVM interoperability with UPF.
 Speaker: Amit Srivastava - Synopsys, Inc.
 Authors: Amit Srivastava - Synopsys, Inc.
Harsh Chilwal - Synopsys, Inc.
Srivatsa Vasudevan - Synopsys, Inc.
11.3Taking Real-value Modeling to the Next Level: Power-aware Verification of Mixed-signal Designs
Every new generation of electronic devices requires higher performance and more sophisticated power management. This poses an exponentially growing verification challenge, especially in the mixed-signal domain. This paper discusses the strategies that we deployed to counter this challenge. Specifically, the focus will be on the techniques in the areas of mixed-signal verification infrastructure, that can translate into verification of any low power mixed signal design.
 Speaker: Subin Thykkoottathil - Analog Devices, Inc.
 Authors: Subin Thykkoottathil - Analog Devices, Inc.
Nagesh N. Ranganath - Analog Devices, Inc.
Jakub Dudek - Analog Devices, Inc.
Nimay Shah - Analog Devices, Inc.
Santosh Singh - Analog Devices, Inc.