WEDNESDAY February 27, 3:00pm - 4:30pm | Monterey/Carmel
EVENT TYPE: REGULAR SESSION
Clifford Cummings - Sunburst Design, Inc.
A further look at how PSS can be adopted for a variety of applications.
|13.1||Coherency Verification & Deadlock Detection using Perspec/Portable Stimulus|
|Many System-on-Chip (SoC) designs for automotive and mobile applications consist of multiple processor cores and IP subsystems that share SoC resources such as memory, system interconnect (IC), and IO subsystems. The effort required to manually create sufficient test suites to verify such a design is significant due to the complexity of the SoC. In this paper, we discuss how Perspec and Portable Stimulus (PS) were used to help shorten the design verification of this type of SoC design in two specific areas: memory coherency and deadlock detection.|
|Speakers:||Phu Huynh - Cadence Design Systems, Inc.
Moonki Jang - Samsung Electronics Co., Ltd.
|Authors:||Moonki Jang - Samsung Electronics Co., Ltd.
Phu Huynh - Cadence Design Systems, Inc.
Jiwoong Kim - Samsung Electronics Co., Ltd.
Hyerim Chung - Samsung Electronics Co., Ltd.
Shai Fuss - Cadence Design Systems, Inc.
|13.2||PSS: The Promises and Pitfalls of Early Adoption|
|PSS suggests an exciting revolution, combining the best of the existing approaches and allowing for different implementations. EDA history suggests a standard accelerates adoption, and early adoption allows you to enjoy the automation sooner, build-up local expertise and even steer the standard to your own needs. However, there are risks of locking into a solution that ultimately does not best match your requirements or that cannot be easily migrated or inter-operate with the future standard. This paper provides a check-list on how to select a technology that allows you to easily migrate to PSS and maximize the capabilities of PSS.|
|Speaker:||Michael Bartley - Test and Verification Solutions
|Author:||Michael Bartley - Test and Verification Solutions
|13.3||Portable Stimulus Driven SystemVerilog/UVM Verification Environment for the Verification of a High-capacity Ethernet Communication Bridge|
|The scope of this paper is to present the steps taken and the challenges faced when using Portable Stimulus(PSS) as an abstraction layer on top of a SystemVerilog/UVM verification environment. PSS is used in conjunction with SystemVerilog/UVM to increase verification efficiency by avoiding “scenario flooding” and keep a tight control of the verification space. All stimuli are defined in the test-bench and they are used to construct scenarios by utilizing a PSS generation model. The flow of the project in this case requires the SV/UVM VE to have an architecture compliant with the PSS mechanics of scenario generation.|
|Speaker:||Andrei Vintila - AMIQ
|Authors:||Andrei Vintila - AMIQ
Ionut Tolea - AMIQ