February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
TUESDAY February 26, 9:00am - 10:30am | Fir
Verification Strategies I
Greg Tumbush - EM Microelectronic - US, Inc.
General recommendations for improving your verification process.

2.1Graphical Topology Info Structure for Constrained Random Verification in SOC/Subsystem Tests
Though the constrained random verification is commonly used at SOC nowadays, many scenarios are still covered by directed tests, for example, the scenarios that require disabling traffic through specific datapath when testing power gating, clock gating or avoiding a missing/broken. With the growth of the number of integrated IPs, the manual setup for the directed tests are becoming more and more a burden to the engineers. To help deploying CRV to these scenarios, this article is proposing a graphical topology info structure, which can easily retrieve the system information, and help better setup constraints for stimulus generation and control checkers.
 Speaker: Evean Qin - Advanced Micro Devices, Inc.
 Authors: Evean Qin - Advanced Micro Devices, Inc.
Richard Bell - Advanced Micro Devices, Inc.
David Chen - Advanced Micro Devices, Inc.
2.2System-level Random Verification: How it Should be Done
With increasing development cost and lower digital gate cost on silicon, Silicon industry is moving towards more general purpose and configurable designs. Broader range of applications are supported with same silicon to increase ROI. This trend is resulting in increasing number of use-cases and many unknown future applications for the same design. We had verification challenge for the design with ~2,000 known use-cases. We have adopted Constrained random verification approach to verify such highly configurable and complex data path design at system level. With the systematic approach and planning, we have achieved quality in reasonable time.
 Speaker: Madhusudan Rathi - Analog Devices, Inc.
 Authors: Madhusudan Rathi - Analog Devices, Inc.
Ashok Chandran - Analog Devices, Inc.
2.3Fully Automated Functional Coverage Closure
This paper mainly aims at the automatic functional coverage closure using a systematic way of writing functional coverage points and leveraging the system functions to know the merged coverage numbers from the previous tests inside the next random test and then regenerating the constraints based on the uncovered functional coverage points.
 Speaker: Manohar Kodi - NVIDIA Corp.
 Authors: Manohar Kodi - NVIDIA Corp.
Sagar Sudam Patil - NVIDIA Corp.
Ranjith Nair - NVIDIA Corp.