February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
TUESDAY February 26, 9:00am - 10:30am | Monterey/Carmel
EVENT TYPE: REGULAR SESSION
SESSION 3
Analog/Mixed-Signal Verification
Chair:
Logie Ramachandran - Accelver Systems Inc.
Verification techniques and methodologies for mixed-signal designs.

3.1Scalable, Re-usable UVM DMS AMS based Verification Methodology for Mixed-signal SOCs
The traditional approach of separate analog and digital verification of current complex mixed-signal SoCs is not sufficient to achieve high quality silicon within given time and resources. In this paper full chip mixed-signal coverage driven constraint random verification environment based on Universal Verification Methodology (UVM) is introduced which supports different abstraction of analog functionality from systemverilog user defined type (SV UDT) to Verilog AMS (VAMS) to transistor model and any combination of these. We explain how a reusable, scalable approach helped to use the best of both analog and digital verification expertise to find issues early and improve overall productivity.
 Speaker: Nilesh Sonara - Broadcom Corp.
 Authors: Nilesh Sonara - Broadcom Corp.
Noorulla Mohammad - Broadcom Corp.
David Stoops - Broadcom Corp.
Poonam Singh - Broadcom Corp.
Joseph Fernando - Broadcom Corp.
Kartik Sudarshana - Broadcom Corp.
3.2Novel Mixed Signal Verification Methodology using Complex UDN
Mixed signal verification using discrete modeling of analog circuits is highly efficient for designs where simulation speed dictates functional verification efficacy. System Verilog provides User Defined Nettype (UDN) for modeling analog nets. Users write customized resolution functions for different types of nets, depending on the nets' behavior. Modeling efficiency can be improved by using standardized resolution functions. To achieve this, we propose a methodology with structure type UDN, i.e. complex UDN, using one standardized resolution function. The resolution function resolves output of drivers according to different scenarios. In addition, this approach enables modeling difficult-to-model circuits like a two-way switch.
 Speaker: Rakesh Dama - Roche Sequencing
 Authors: Rakesh Dama - Roche Sequencing
Ravi Reddy - Roche Sequencing
Andy Vitek - Roche Sequencing
3.3Translating and Adapting to the “Real” World: SerDes Mixed Signal Verification using UVM
This paper talks about building configurable UVM testbench and talks about techniques to effectively model the translator blocks to handle the "real" valued data types, for mixed signal designs like SerDes PMA. We talk about methodologies to improve the UVM sequence architecture and also how to bring in additional intelligence to the testbench by creating components which model the critical features like pre-emphasis and adaptation. These techniques can be extended to any mixed signal design with one or multiple data lanes.
 Speaker: Akhila Madhu Kumar - Intel Corp.
 Authors: Akhila Madhu Kumar - Intel Corp.
Karl Herterich - Intel Corp.