JT Longino - Synopsys, Inc.
Per Bjesse - Synopsys, Inc.
With the proliferation of different hardware architectures with an increased focus on Artificial Intelligence (AI) and compute intensive designs, the development and customization of datapath units (ALU, FPU, DSP etc) has seen a significant rise. At the same time, power, performance, area coupled with safety and security are posing unique challenges for validation and verification of system-on-chip (SoC). High assurance verification in a constantly shrinking time-to-market scenario is a massive challenge that can be addressed efficiently through formal verification technologies and methodologies.
Over the last few years we have seen formal verification become a main stream solution for verification engineers. While it is generally well accepted that formal verification can help find more bugs and reduce turn-around-time in many problem domains, scalability and convergence challenges still persist. The challenges are complex spanning both datapath and control.
Whereas, historically, there hasn't been a wide adoption of formal for datapath mainly due to the lack of good commercial solutions, this is no longer the case as recent technological and methodology advancements have shown. At the same time control verification which contributes to most amount of bugs has been a sweet spot for formal but with serial dataflow designs this is still a massive challenge.
In this tutorial, the industry leaders in formal verification will introduce, teach and provide a detailed methodology and insight to successfully conquer some of the most challenging problem in both the control and datapath verification domains. Specifically, the following topics will be covered in depth.
- Why exhaustive formal verification is must-have for specific datapath intensive designs
- Recent technological and methodology advancements for better and faster convergence
- New formal application domains to increase Verification ROI
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