February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
TUESDAY February 26, 10:30am - 12:00pm | Gateway Foyer
Poster Session
John Dickol - Samsung Austin R&D Center

4.1Efficient Hierarchical Low Power Verification of Custom Designs using Static and Dynamic Techniques
As mixed SoCs (ASIC + FPGA) are gathering momentum because of the ease of custom programming, low power verification is becoming increasingly imperative. The biggest challenges faced are that the industry leading tools for both dynamic and static verification are not tailor-made for the custom based designs. The custom designs start from the schematic which is then written out into a netlist using certain tools. UPF creation is tricky. Also there is no defined methodology for low power verification of custom blocks. The paper describes a methodology for efficient low power verification ensuring that subtle bugs do not escape silicon.
 Speaker: Himanshu Bhatt - Synopsys, Inc.
 Authors: Himanshu Bhatt - Synopsys, Inc.
Archanna Srinivasan - Intel Programmable Solutions Group
Chong Lee Kuay - Intel Programmable Solutions Group
4.2Interfacing Python with a SystemVerilog Test Bench
As a design verification engineer, there is a constant need to use foreign languages like C, C++ or MATLAB for complex calculations that SystemVerilog may not be able to handle easily. MATLAB is widely used to create signal processing reference models because of the availability of numerous mathematical libraries. Apart from its libraries, it can be used to easily plot graphs and calls to a MATLAB function can be made from a SystemVerilog test bench. This paper discusses how Python can be seamlessly integrated with SystemVerilog as an alternative to MATLAB.
 Speaker: Lakshay Grover - Analog Devices, Inc.
 Authors: Lakshay Grover - Analog Devices, Inc.
Kaushal Modi - Analog Devices, Inc.
4.3SystemC FMU for Verification of Advanced Driver Assistance Systems
Integrated framework to simulate electronic system with the mechanical parts of a heterogeneous automotive system is presented. The electronic system, consisting of many Electronic Control Units (ECUs), is modeled to simulate the system functionality. The recently developed Functional Mock-up standard approach is used to have a model for a complex cyber-physical automotive system. The framework simulates real system including Hardware (HW) and Software (SW) to run on the ECUs. It allows Co-development of the automotive system while the mechanical system is in the loop. The development cycle for the automotive system could be greatly shortened using the proposed framework.
 Speaker: Magdy A. El-Moursy - Mentor, A Siemens Business
 Authors: Keroles K. Khalil - Mentor, A Siemens Business
Magdy A. El-Moursy - Mentor, A Siemens Business
4.4Predicting Bad Commits
This paper explores the feasibility of predicting bad commits before they happen and how this capability can be used in a continuous integration context. Using standard machine learning techniques we demonstrate that it is possible to achieve 34% precision in bug prediction. That means 1 in 3 predictions are correct. Key to achieving this outcome is the combination of PinDown and Code Maat. PinDown is an automatic debugger of regression test failures. Code Maat is a free tool for mining and analyzing data from version control. The data is from a commercial large team ASIC project.
 Speaker: Christian Graber - Verifyter AB
 Authors: Christian Graber - Verifyter AB
Daniel Hansson - Verifyter AB
Adam Tornhill - Empear
4.5Dynamic Control Over UVM Register Backdoor Hierarchy
Recent times, SoC complexity has increased manifold. A major reason is the increased feature addition into a single chip for multiple customer requirements. This has made the programming of the chip complex. For DV, proper programming is essential to get the chip into the required state. This programming consumes much of the simulation time, especially if done through some slow peripherals like serial ports. Backdoor access is an advantage here but will not directly solve all the use-cases. This paper discusses how to dynamically change the backdoor hierarchy for a register access, using callbacks, from one of our use-case perspectives.
 Speaker: Roy Vincent - Analog Devices, Inc.
 Authors: Roy Vincent - Analog Devices, Inc.
Unnikrishnan Nath - Analog Devices, Inc.
Ashok Chandran - Analog Devices, Inc.
4.6An Efficient Analog Fault-injection Flow Harnessing the Power of Abstraction
Designing an IC for functional safety according to the ISO~26262 standard requires one to identify failure modes and their associated probability of occurrence to assess the possible impact on the realization of the safety goals. Fault-injection is a recommended approach for the identification of failure modes. This paper proposes a multi-tier approach relying on the power of abstraction to limit the overall number of fault-injection simulations to realize and to speed-up their execution by switching to more efficient models of computation.
 Speaker: Enrico Fraccaroli - Univ. of Verona
 Authors: Renaud Gillon - ON Semiconductor Belgium BVBA
Enrico Fraccaroli - Univ. of Verona
Franco Fummi - Univ. of Verona & EDALab s.r.l.
4.7Transaction Recording Anywhere Anytime
This paper will educate the reader on how to use transaction recording for effective debug. Transaction recording has been available for years, with various APIs available in various states of usability. This paper will solidify the usage of the APIs and enable readers to build their own transaction based verification environments.
 Speaker: Rich Edelman - Mentor, A Siemens Business
 Author: Rich Edelman - Mentor, A Siemens Business
4.8Flex-Checker a One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding
Abstract-This paper aims at defining a methodology for a composite checker/scoreboard called 'flex checker' that provides test bench writers a solution which can adapt to ever changing design configurations. The flex checker also provides a solution which is portable across blocks, sub-blocks and chip level environments. It has a unique "transaction trace checking" which checks transactions at multiple internal nodes before reaches end points. The flex checker is equipped to record and dump vital statistics related to the latency, bandwidth and throughput of the system in report phase.
 Speaker: Saad Zahid - Arteris, Inc.
 Authors: Saad Zahid - Arteris, Inc.
Chandra Veedhi - Arteris, Inc.
Sumit Dhamanwala - Arteris, Inc.
4.9An Enhanced Stimulus and Checking Mechanism on Cache Verification
Cache verification has been regarded as one of the most challenging problems due to increasing design complexity. In this paper, we demonstrate a flexible UVM-based verification solution to cache. In order to fulfill cache's typical scenarios, an elaborately-designed layered sequence using the feedback mechanism is adopted. Scoreboard based on mesh streams is used for end-to-end data checking. Taking into order and correspondence into consideration, we demonstrate several customized checking policies.
 Speaker: Chenghuan Li - MediaTek, Inc.
 Authors: Chenghuan Li - MediaTek, Inc.
Xiaohui Zhao - MediaTek, Inc.
Yunyang Song - MediaTek, Inc.
4.10SystemVerilog Format of Portable Stimulus
Portable Test and Stimulus Standard defines two input formats, DSL and C++. A portable stimulus specification can be created accordingly. This specification can be regenerated and run on different platforms like simulation, emulation, post-silicon, etc. Simulation platform usually starts earlier than others. It's naturally where the specification is developed. The majority of simulation environments are in SystemVerilog. This mismatch of programming language increases overhead and reduces the value added by portable stimulus. A SystemVerilog input format is defined in this paper. It is semantically identical to other two input formats and eliminates the language mismatch. It's prototyped and demonstrated feasible.
 Speaker: Wayne Yun - Advanced Micro Devices, Inc.
 Authors: Wayne Yun - Advanced Micro Devices, Inc.
David Chen - Advanced Micro Devices, Inc.
Theta Yang - Advanced Micro Devices, Inc.
Evean Qin - Advanced Micro Devices, Inc.
4.11Clock Domain Crossing Verification in Transistor-level Design
Clock domain crossing (CDC) is one of the most challenging issues to modern verification engineers. There are lots of commercial tool for verifying CDC with RTL/Gate-level design, but none of them can analyze designs in transistor-level description. In this paper, methodology for transistor-level CDC analysis is addressed. The first part of the paper shows a workaround solution using Synopsys NanoTime and its limitations. With the lessons of the commercial workaround solution, transistor-level CDC verification tool is described. Through experiments, it is shown that the proposed CDC verification tool generates the higher coverage and performance compared to commercial workaround solution.
 Speaker: Hyungjung Seo - Samsung Electronics Co., Ltd.
 Authors: Hyungjung Seo - Samsung Electronics Co., Ltd.
KwangSun Kim - Samsung Electronics Co., Ltd.
YoungRok Choi - Samsung Electronics Co., Ltd.
Jihwan Kim - Samsung Electronics Co., Ltd.
SeungBum Ko - Samsung Electronics Co., Ltd.
4.12Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications
Multiplication is the core operation used in the linear piecewise approximation. In this paper, the logarithmic number system (LNS) is exploited to design a low power and high speed multiplier-adder-converter (MAC). MAC is included in the piecewise linear polynomial approximation to achieve efficient power design with large operand input size. Hardware implementation and synthesis are performed using 90 nm CMOS technology. Up to 30% and 55% reduction in power and delay are attained with the proposed design. MAC considerably improves the power delay product by up to 70% as compared to the well-known multipliers.
 Speaker: Magdy A. El-Moursy - Mentor, A Siemens Business
 Authors: Magdy A. El-Moursy - Mentor, A Siemens Business
Dina Ellaithy - Electronics Research Institute
Amal Zaki - Electronics Research Institute
Abdelhalim Zekry - Electronics Research Institute
4.13Verification of Accelerators in System Context
Hardware can be used to accelerate operations on a processor, by taking some of the processing load originally handled by software. These accelerators need to be verified in the traditional manner, but will also benefit from being verified in the context of the larger body of software they run with. This session will explore the development and verification of a Tensorflow accelerator. Tensorflow graphs are typically written in Python. We will describe how to verify the accelerator in the context of the execution of the complete Tensorflow graph in Python on both host based and embedded processor contexts.
 Speaker: John Stickley - Mentor, A Siemens Business
 Author: Russell A. Klein - Mentor, A Siemens Business
4.14Introducing your Team to an IDE
Text editors like Vi and EMACS have been replaced by Integrated Development Environments (IDEs) for developing applications in software languages such as C, C++, and Java. IDEs boost code-development productivity by putting information from across large codebases at the user's fingertips, prompting users with context-sensitive information, providing navigation based on the semantics of the language, and in general simplifying the process of working with large and complex software projects. This paper introduces the benefits of an IDE in an HDL environment, and discusses challenges and strategies used to adopt an IDE.
 Speaker: Steven Dawson - Consultant
 Authors: Steven Dawson - Consultant
Matthew Ballance - Mentor, A Siemens Business
4.15Using UPF Information Model APIs to Write Re-usable Low Power Testbenches and Customized Coverage Models for Low Power
Low Power Testbenches with UPF today are mostly designed to have a one-way communication with the UPF objects with no way to monitor their state. The UPF Information model APIs provide a consistent way to access UPF information at compile time (using TCL queries) and runtime (using System Verilog APIs). This paper explores the applications of the UPF Information model APIs namely writing reusable Low Power testbenches with the ability to monitor and control the UPF objects and build customized coverage models for Low Power. The possible impact on simulation performance is also examined.
 Speaker: Shreedhar Ramachandra - Synopsys, Inc.
 Authors: Shreedhar Ramachandra - Synopsys, Inc.
Himanshu Bhatt - Synopsys, Inc.
4.16In Pursuit of Faster Register Abstract Layer (RAL) Model
The UVM RAL model is good for small testbenches but with system level testbenches containing thousands of registers, it impacts the performance and adds significant load to the simulator. To overcome these performance issues, we have developed several alternative RAL models. The underlying approach in the first two models is to optimize the number of handles to register classes and to store register information in associative-array based lookup tables. There is also a third model which uses the register and field classes written in C++ instead of “uvm_reg” and “uvm_reg_field” classes.
 Speaker: Anmol Rana - Agnisys, Inc.
 Authors: Anmol Rana - Agnisys, Inc.
Bhagwan Jha - Agnisys, Inc.
Harjeet Singh Sangha - Agnisys, Inc.
4.17Verification Reuse for a Non-transaction Based Design Across Multiple Platforms
We are experiencing an era of digital disruption where the Big Data, IoT and mobility are transforming businesses. Servers are prone to this change and their architecture has become more complex. At HPE, we have to react fast and adapt our server portfolio and offer multiple products to satisfy our customer needs, driving a huge need for reuse. A large percentage of the design that is non-transaction based has created the need for a highly configurable verification environment. This paper will explore the techniques applied to achieve high reusability and a tool to manage the coverage for non-transaction based stimulus.
 Speaker: Pablo Salazar - Hewlett Packard Enterprise
 Authors: Luis Li - Hewlett Packard Enterprise
Pablo Salazar - Hewlett Packard Enterprise
Andres Cordero - Hewlett Packard Enterprise
4.18Conquer the Graphics Legacy: Develop the Customized UVM VIP Embedded a Cycle-based C++ Reference Model
Graphics verification usually adopts the cycle-based C++ simulation model (CSIM) to represent the functional behavior of a DUT. The legacy block-level testbench uses a Verilog BFM to interact with the CSIM which takes the client behavior role. The bridge between BFM and CSIM is either the direct programming interface (DPI) or SystemC proxy. This approach works well for years, but it really has several issues too challenging for us to migrate the legacy testbench into UVM testbench. This paper will discuss a legacy cases study and then illustrate a practical approach for customized UVM VIP embedded in the CSIM.
 Speaker: Roman Wang - Advanced Micro Devices, Inc.
 Author: Roman Wang - Advanced Micro Devices, Inc.
4.19Timing Coverages: An Approach to Analyze Performance Holes
This paper presents Timing coverages as an approach in analyzing performance bottlenecks with respect to design as well as finding in holes with respect to performance verification.A timing coverage model is implemented with cover bins configured in form of delay values ranging from minimum supported timing to maximum supported timings.If a typical cover bin is created with the minimum allowed value from the specification, the coverage report with that bin as a coverage hit, will ensure that a typical scenario testing the minimum timing of DUT exists in verification suite and is testing the performance aspect of that DUT.
 Speaker: Vikas Makhija - Synopsys India Pvt. Ltd.
 Authors: Surbhi Kalia - Synopsys India Pvt. Ltd.
Shubhadeep Karmakar - Synopsys India Pvt. Ltd.
Vikas Makhija - Synopsys India Pvt. Ltd.
Apoorva Mathur - Synopsys India Pvt. Ltd.
4.20Novel Approach to ASIC Prototyping
Emulation provides respectable acceleration at IP-level. But due to larger design and increased complexity at subsystem/SoC level, design speed becomes a bottleneck for validation. ASIC prototyping can be used as a platform to achieve early prototypes that run practically at real-time speeds and perform early validation of hardware-IPs and software-hardware interaction. With a good understanding of the FPGA platform, tradeoffs can be made to reuse test bench collateral from emulation that match design and validation requirements to improve model build turnaround times. It's also imperative to make sure that FPGA platforms are available for all users at an organizational level.
 Speakers: Suresh Balasubramanian - Intel Corp.
Mohamed Saheel Nandikotkur Hussainsaheb - Intel Corp.
 Authors: Suresh Balasubramanian - Intel Corp.
Vijayakrishnan Rousseau - Intel Corp.
Mohamed Saheel Nandikotkur Hussainsaheb - Intel Corp.
4.21Emulation Testbench Optimizations for Better Hardware Software Co-Validation
With tighter time to market schedules it is not enough if the silicon is bug free, it is also required for the software stack to be ready in order to launch the product. In order to validate the hardware software interaction it is mandatory that certain level of software validation is done on the actual hardware before silicon which is achieved by the use of an emulator This paper discusses about the inefficiencies in an emulation testbench which slow down the hardware software validation and ideas to improve them.
 Speakers: Vijayakrishnan Rousseau - Intel Corp.
Srikanth Reddy Rolla - Intel Corp.
 Authors: Vijayakrishnan Rousseau - Intel Corp.
Suresh Balasubramanian - Intel Corp.
Srikanth Reddy Rolla - Intel Corp.
Mohamed Saheel Nandikotkur Hussainsaheb - Intel Corp.
4.22How to Create Reusable Portable testing and Stimulus Standard (PSS) Verification IP
With years of experience using the PSS concepts on dozens of projects, and multiple platforms we identified communality, developed a consistent methodology, and even codified some of the best practices in a common library. This paper answers many questions that a user may ask himself before writing his first PSS file: - How to ensure code modularity and future integration vertically and horizontally? - Any recommended coding styles for PSS VIP to be consistent and flexible for enhancements? - How do I best serve test-writer needs? - What can be provided in standard library and how will it look like?
 Speaker: Sharon Rosenberg - Cadence Design Systems, Inc.
 Author: Sharon Rosenberg - Cadence Design Systems, Inc.
4.23Utilizing Technology Implementation Data in Blended Hardware/Software Power Optimization
This presentation will illustrate methodologies for dynamic power analysis and UPF verification, linking software executing on the processors of a SoC to silicon technology. We will compare different types of toggle formats, allowing the selection of a time-window of interest. With sufficiently lossless compression original full data set toggle formats users can dive into more detail, feed them into logic synthesis, annotating power estimates back into the analysis of software as well as the dynamic behavior as executed in emulation. Special attention will be given to optimizing the interface between power estimation from .lib representation to emulation using parallelization.
 Speaker: Theodore Wilson - Wilson Consulting
 Authors: Theodore Wilson - Wilson Consulting
Frank Schirrmeister - Cadence Design Systems, Inc. & Vayavya Labs Pvt., Ltd.
4.24System Model – A Testbench Library Component Aided for Emulating User Interaction
To perform exhaustive verification of CPU cores, we need a capability in tests to control external stimuli and monitor internal system events. The existing solutions in the industry are mainly ad-hoc and dedicated for one or another type of processor and there lacks such an instruction-set-independent testbench component to work within different types of processors. For this purpose, we have created a universal testbench component. The primary use-case of the System Model is to interpret "special" stimulus events as triggers and inject the corresponding asynchronous events into the processor cores.
 Speaker: Hussain Wadia - Advanced Micro Devices, Inc.
 Author: Hussain Wadia - Advanced Micro Devices, Inc.
4.25Moving Beyond Assertions: An Innovative Approach to Low-power Checking using UPF Tcl Apps
One of the traditional yet effective way to verify the design is to write SV assertions. Verifying the low-power intent of the design using SV assertions is not straightforward because there is disconnect between the traditional RTL and low-power objects. In this paper we are going to demonstrate with relevant examples and case studies that how we can leverage UPF 3.0 information model TCL query functions and tool provided CLI commands can be used to do low-power checking of the design.
 Speaker: Madhur Bhargava - Mentor, A Siemens Business
 Author: Madhur Bhargava - Mentor, A Siemens Business