MONDAY February 25, 3:30pm - 5:00pm | Oak
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EVENT TYPE: SHORT WORKSHOP
SESSION 5SWEnabling System-Level Security Verification through the Chip Design Lifecycle
Jason Oberg - Tortuga Logic
Jonathan Valamehr - Tortuga Logic
With the seemingly continuous discovery of vulnerabilities such as Meltdown and Spectre, a new awareness has been built around the fact that microarchitectural design choices can enable system-wide exploits. Innocuous changes to a processor’s design meant to improve performance and other tradeoffs can inadvertently introduce security issues. Because of this, security is at the forefront of every hardware design’s priorities. Unfortunately, the current set of tools and techniques for hardware security verification are inadequate at finding the most elusive hardware security vulnerabilities. A major reason for the unsuccessful identification of hardware security vulnerabilities is the lack of a Secure Development Lifecycle (SDL), which is a well-known and followed practice in the software world to employ the latest techniques and tools to find software security vulnerabilities throughout the software design lifecycle. Without an established SDL, engineers are left to manually review state diagrams, manually review design files, and postulate on design and architecture specifications. This ends up being extremely time-consuming, is not automated and thus susceptible to human error, and consequently leaves systems susceptible to costly vulnerabilities especially due to changes introduced late in the hardware design lifecycle. In order to create a successful SDL for hardware designs, several challenges need to be addressed. In this workshop, we discuss the state of hardware security in general, then discuss how microarchitectural changes to a design can affect system security. We will also discuss common hardware security concerns. We then discuss common hardware security verification techniques, as well as their benefits and drawbacks. Next, we will present the best-in-class techniques and methodologies for understanding the security ramifications of any microarchitectural/architectural change that is applied to a design, and how these techniques can be employed across the entire design lifecycle, drastically increasing the chance of identification. Lastly, we will present an example security analysis on a real world hardware design using the discussed techniques. The security analysis will be performed as a live demo to showcase the entire process from threat model specification to tangible results.
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