TUESDAY February 26, 3:00pm - 4:30pm | Fir
EVENT TYPE: REGULAR SESSION
Dave Rich - Mentor, A Siemens Business
Applying Big Data and Machine Learning to your verification process.
|6.1||Big Data in Verification: Making Your Engineers Smarter|
|Big Data is getting a lot of press these days but does it really apply to ASIC verification efforts? HPE has found that it does apply and can be instrumental in helping make smarter decisions. In this paper, we will share our view of using Big Data concepts in the ASIC verification domain, highlighting several specific examples of how easy it is for the audience to get started with their own Big Data analysis. We will also share our ideas on where we see larger Big Data opportunities being able to help our verification efforts in the future.|
|Speaker:||Alan J. Pippin - Hewlett Packard Enterprise
|Authors:||David Lacey - Hewlett Packard Enterprise
Alan J. Pippin - Hewlett Packard Enterprise
Ron Thurgood - Hewlett Packard Enterprise
Ed Powell - Hewlett Packard Enterprise
Mike McGrath - Hewlett Packard Enterprise
Alex Wilson - Hewlett Packard Enterprise
|6.2||Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms|
|Analyzing and prioritizing the unverified features in the design significantly affects the engineering time taken to converge a design's coverage goal. This research focuses on optimization of constrained random verification using machine learning algorithms. Machine learning is used to modify randomization constraints during simulation runtime in response to instrumentation of the DUT. The enhanced environment resolves some limitations of the previous efforts proposed in a DVCon 2017 paper by Nelson. Simpler algorithms such as linear regression and more complicated algorithms such as artificial neural networks augment the simulation as it attempts to predict useful stimulus.|
|Speaker:||Eldon G. Nelson - Synopsys, Inc.
|Authors:||Sarath Mohan Ambalakkat - Univ. of Minnesota, Twin Cities
Eldon G. Nelson - Synopsys, Inc.
|6.3||Using Machine Learning in Register Automation and Verification|
|Machine Learning concept has been leveraged to help users create IP and SoC specification. Having defined the specification, one can automatically create design code and verification environment. We present a novel way to capture design intent vis-à-vis addressable registers and sequences, use ML algorithms to identify patterns in the natural language description, and to automate the whole design and the verification environment from it. We also present our experience in converting System Verilog Assertions into plain English language using ML algorithms.|
|Speaker:||Nikita Gulliya - Agnisys, Inc.
|Authors:||Nikita Gulliya - Agnisys, Inc.
Abhishek Bora - Agnisys, Inc.
Nitin Chaudhary - Agnisys, Inc.
Amanjyot Kaur - Agnisys, Inc.