March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY February 26, 3:00pm - 4:30pm | Monterey/Carmel
EVENT TYPE: REGULAR SESSION

SESSION 7
Verification Strategies II
Chair:
Kamel Belhous - Teradyne, Inc.
More general recommendations for improving your verification process.

7.1Using Save/Restore is Easy, Right? A User's Perspective on Deploying Save/Restore in a Mature Verification Methodology
ASIC designs today are growing in size, with the use of interposers and multiple chiplets that need to be simulated. As simulation topologies grow, the simulation performance suffers greatly, leading to very long test times. In many cases, the initialization sequence does not perform anything unique, making the running of this phase of the simulation necessary but not valuable. Our team has fully integrated the save/restore technology into our verification methodology and this paper will explore how we accomplished this integration, the challenges we faced, how we solved those challenges, and the real benefits we have observed will be presented.
 Speaker: Ron Thurgood - Hewlett Packard Enterprise
 Authors: Ed Powell - Hewlett Packard Enterprise
Ron Thurgood - Hewlett Packard Enterprise
Aneesh Samudrala - Hewlett Packard Enterprise
7.2Automation of Reusable Protocol-agnostic Performance Analysis in UVM Environments
Performance analysis of a design requires significant effort simply to measure the figures of merit. In order for performance to take a principal role in design and verification processes, the total process of measuring, analyzing, and optimizing performance needs to be easy as possible. We developed a framework named Autoperf that uses design metadata from the verification environment to generate analyses of digital memory system performance against a general and extensible performance model. Using this model, we can process simulation results in a protocol-agnostic way and produce uniform performance measurements across all interfaces, protocols, and devices.
 Speaker: Daniel P. Carrington - Hewlett Packard Enterprise
 Authors: Daniel P. Carrington - Hewlett Packard Enterprise
Alan J. Pippin - Hewlett Packard Enterprise
Timothy Pertuit - Hewlett Packard Enterprise
7.3Yikes! Why is My SystemVerilog Still So Slooooow?
(Note: Full abstract attached. This is only an intro) In the 2012 edition of this topic we observed that thousands of engineers were cranking out SystemVerilog code but often found the simulation of that code ran slower than expected. We offered a number of testbench-focused recommendations for optimizing that code. Since then, millions more lines of code have been generated, simulators have become faster, but the question engineers raise is often the same with one new word: “Why is my SystemVerilog still so slow?”
 Speaker: Clifford E. Cummings - Sunburst Design, Inc.
 Authors: Clifford E. Cummings - Sunburst Design, Inc.
John Rose - Cadence Design Systems, Inc.
Adam Sherer - Cadence Design Systems, Inc.