February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
THURSDAY February 28, 1:00pm - 2:30pm | Oak
KEYWORD: SYSTEMVERILOG FOR VERIFICATION AND/OR DESIGN
EVENT TYPE: SHORT WORKSHOP
SESSION 7SW
Be a Sequence Pro to Avoid Bad Con Sequences

Speakers:
Jeff Montesano - Verilab, Inc.
Jeff Vance - Verilab, Inc.
Organizers:
Mark Litterick - Verilab, Inc.
Jeff Vance - Verilab, Inc.
Jeff Montesano - Verilab, Inc.

Workshop Motivation

The Universal Verification Methodology (UVM) is widely accepted as the industry standard for verification of chip designs. While UVM has many features to help with the challenges of verifying complex designs, UVM sequences for stimulus arguably have the most impact on verification quality. Despite the maturity and widespread success of UVM across many projects, evidence has shown that UVM sequences are typically not applied to their fullest potential. This is largely due to a lack published resources with guidance on how to define large-scale sequence libraries to solve more complex verification challenges. The consequences are seen in typical projects where large collections of ad-hoc sequences create additional problems for engineering teams instead of helping them tape out bug-free designs on schedule. These challenges include additional unnecessary complexity, insufficient control of stimulus for tests, and limited reuse. 

In addition to the general problems of ad-hoc sequence libraries, UVM sequences are vital to success in several ways that are often overlooked. There is little guidance on how to apply sequences for controlling continuous streams of data over time.  This includes digital streaming data, analog stimulus, and clock generation. Sequences also serve as an API to engineering teams who must create verification plans, manage test regressions, triage debug tasks, report project status, and manage risks to meet schedules. An inadequate sequence API to support these tasks frequently creates workflow bottlenecks as teams struggle to transfer knowledge, isolate problems, and transparently report status to project stakeholders.

Finally, UVM sequences will continue to be used by teams that are considering adopting the newer Portable Stimulus methodology. In order to successfully integrate high-level portable stimulus with a simulation-based testbench, an adequate UVM sequence API is vital.
This workshop addresses all these problems by providing guidelines based on extensive project experience applying UVM sequences in a variety of situations, from small block-level testbenches to complex integrations with challenging reuse and usability demands.


Workshop Content

 
This lecture-style workshop provides guidelines that improve a verification team’s ability to face the challenges of managing large-scale sequence libraries, while improving project efficiency, communication, and visibility of project status.

Sequence Library Guidelines
We outline a sequence API layering strategy that provides better encapsulation for UVCs, reduces complexity for test writers, and allows better reuse of sequences within a sequence library (and between derivative projects). We then give implementation guidelines that most impact the problems of complexity, control and reuse in a sequence library. These guidelines include a comparison of different constraint model techniques and recommendations for which are most ideal for certain testbench goals. Examples for applying each guideline build on each other to show how this results in powerful system-wide stimulus control that can’t otherwise be achieved with ad-hoc collections of sequences.

Sequences for Streaming Data
We give guidelines on controlling continuous streams of values over periods of time. Examples include clock generation with jitter and skew, steaming data to external digital interfaces, and analog stimulus to analog-to-digital converters. In these cases, we need fine grained control over the input patterns. This allows us to validate interesting combinations of stimulus that might otherwise be hard to do from a UVM sequence. This tutorial shows how to achieve this control in a testbench while giving the user a sequence API that is consistent with standard UVM practice.

Improving Verification Productivity
In addition to managing the technical challenges of large sequence libraries, we show how to use sequences to improve verification productivity. We show how to use sequences to isolate design features for easier debug, regression management, and better coverage control. These techniques directly improve the visibility of project status to stakeholders and allow flexibility to adapt to changing schedules.

Portable Stimulus Considerations
We show how a well-designed sequence API is vital for adoption of a Portable Stimulus workflow. Teams who are currently using portable stimulus, or are considering using it in the future, can save time and effort by ensuring upfront that their sequence library directly supports both UVM test suites and portable stimulus.

 

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