March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY February 27, 10:00am - 12:00pm | Oak

Hybrid Verification Environments
Josh Rensch - Intel Corp.
Combining multiple verification platforms for verification.

8.1OS-aware IP Development Methodology
In this paper, we propose OS-aware IP development methodology. The main purpose of this methodology is to enable both SW/HW co-design and co-verification prior to building matured SoC, thus contributing to the reduction of total development period for mobile APs by securing early-verified SW/HW IP.
 Speaker: Hyunjae Woo - Samsung Electronics Co., Ltd.
 Authors: Hyunjae Woo - Samsung Electronics Co., Ltd.
Woojoo Kim - Samsung Electronics Co., Ltd.
Youngsik Kim - Samsung Electronics Co., Ltd.
Seonil Brian Choi - Samsung Electronics Co., Ltd.
8.2High-speed Interface IP Validation based on Virtual Emulation Platform
As the complexity and the speed of HSI (High Speed Interface) IPs are rapidly increasing with every generation, it is becoming harder to functionally validate the HSI IPs within given schedules. To achieve this, various methodologies are utilized to completely validate the HSI IP. One of commonly used methods is Field Programmable Gate Array (FPGA). However, using an FPGA still has some challenges such as visibility, high effort to implement design and high turn-around-time (TAT). This paper suggests virtual emulation platform to address the above problems. Virtual emulation is used to test the design under test (DUT) with OS-level applications on a virtual machine and has the advantages of full-blown emulation like full-visibility, real scenario and fast speed.
 Speaker: Jaehun Lee - Samsung Electronics Co., Ltd.
 Authors: Jaehun Lee - Samsung Electronics Co., Ltd.
Daeseo Cha - Samsung Electronics Co., Ltd.
Sungwook Moon - Samsung Electronics Co., Ltd.
8.3How to Test the Whole Firmware/Software when the RTL can’t fit the Emulator
Pre-silicon firmware and software (FW/SW) testing is a necessary for all silicon companies. One of the biggest challenge is the RTL cannot fit the emulator. In verification, it is a common practice to black box unused logics in the RTL to reduce gate counts. However adopting this approach in emulation has unique challenges due to the difference in the architecture of UVM testbench vs FW/SW. In this paper, we will present our strategy on how to run the full FW/SW on black boxed RTL in the emulator. We will discuss the benefit of our strategy over using Virtual Platform.
 Speaker: Horace Chan - Microchip Technology Inc.
 Authors: Horace Chan - Microchip Technology Inc.
Byron Watt - Microchip Technology Inc.
8.4NVMe Development and Debug for a 16 x Multicore System
Non-Volatile Memory Express (NVMe) is an open logical device interface specification for accessing non-volatile storage media attached via a PCI Express (PCIe) bus. As a logical device interface, NVMe has been designed from the ground up to capitalize on the low latency and internal parallelism of solid-state storage devices. This presentation will introduce the verification challenges for NVMe and discuss verification approaches, combining simulation and emulation to achieve verification acceleration using Accelerated Verification IP for PCIe, achieving 300x-700x acceleration over simulation for 50-100MGate design transacting 20 Transaction Layer Packets (TLPs).
 Speakers: Ankit Ganguly - Cadence Design Systems, Inc.
Sangeetha Chandran Sarala - Cadence Design Systems, Inc.
 Authors: Soummya Mallik - Microchip Technology Inc.
Arindam Guha - Cadence Design Systems, Inc.
Raj Mathur - Cadence Design Systems, Inc.
Frank Schirrmeister - Cadence Design Systems, Inc. & Vayavya Labs Pvt., Ltd.