THURSDAY February 28, 1:00pm - 2:30pm | Fir
Wei-hua Han - Synopsys, Inc.
Design complexity growth has inspired new techniques to accelerate digital simulation of circuits by taking full advantage of high-performance hardware resources available to verification teams. Latest techniques include fine-grained parallelism, which can significantly reduce simulation turn-around time by automatically partitioning the design to execute on multiple processor cores, and simulation acceleration, which accelerates the verification of block and platform level IP by integrating fast simulation with the specialized, high-performance hardware provided by fast emulation systems.
This workshop reviews new simulation acceleration technology for Synopsys VCS and how it will enable verification engineers to speed up the digital simulation of standard UVM testbenches, including all existing verification requirements, through the seamless integration of VCS and the Synopsys ZeBu Server emulation system. The workshop will present the use models and basic tool options required to enable simulation acceleration within a regular VCS environment, the SystemVerilog constructs used, and the available debug and profiling capabilities. For different verification needs, we will analyze how the different constructs and use-models provide trade-offs between ease of use, simulation performance and hardware utilization. We will conclude with an AXI Master/Slave example showing code snippets to illustrate the use models and how this new simulation acceleration technology can improve digital simulation performance for your design.
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