March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
WEDNESDAY February 27, 10:00am - 12:00pm | Fir
EVENT TYPE: REGULAR SESSION
SESSION 9
Advancements in Clock Domain Crossing Verification
Chair:
Dan Benua - Cadence Design Systems, Inc.
New techniques to analyze and verify CDC challenges.

9.1Fully Hierarchical CDC Analysis using Comprehensive CDC Meta-Database
This paper introduces an innovative systematic approach to enable accurate hierarchical CDC verification. The approach uses IP-reuse principles and a divide-and-conquer paradigm to remove redundancy in the CDC verification effort. Rather than using boundary models, this approach uses a new comprehensive CDC Meta-database. This Meta-database stores comprehensive CDC-relevant information such as CDC components, CDC environment, CDC assumptions, clock-tree, boundary connectivity and CDC configurations. This allows consistency checks between IP and SoC to catch CDC-intent mismatches. We’ll show how these CDC meta-database can save efforts and time in SoC CDC analysis and the real application result throughout IP-to-block and block-to-top flow.
 Speaker: Youngchan Lee - Samsung Electronics Co., Ltd.
 Authors: Youngchan Lee - Samsung Electronics Co., Ltd.
Youngsik Kim - Samsung Electronics Co., Ltd.
Seonil Brian Choi - Samsung Electronics Co., Ltd.
Vikas Sachdeva - Real Intent, Inc.
9.2A Systematic Take on Addressing Dynamic CDC Verification Challenges
In this paper, we propose a methodology for ensuring reliability of synchronizers on CDC paths by verifying their protocols/assumptions using both Formal and Simulation environments in a systematic manner. The approach not only automates progression of setup, constraints from CDC to Formal and Simulation, but also correlates their results. To achieve this, we have come up with a technique of adding hooks to Formal, Simulation for extracting information and associating to CDC results. The approach has been automated and demonstrated on real life designs to show significant reduction in verification effort, which helps achieve faster design closure.
 Speaker: Kurt Takara - Mentor, A Siemens Business
 Authors: Sukriti Bisht - Mentor, A Siemens Business
Sulabh K. Khare - Mentor, A Siemens Business
Ashish Hari - Mentor, A Siemens Business
9.3Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy
In this paper we will show how an automated, “modal” CDC analysis can be used to exhaustively verify all CDC issues in all test and operational modes of a large SoC with multiple IPs. Specifically, modal CDC analysis con-figures the design as a set of operational modes and then runs CDC analysis on each modal version of the design. This accomplishes several things: • Captures the modal nature of the design • Improves multi-mode analysis accuracy • Reduces complexity and “pessimism”
 Speaker: Kurt Takara - Mentor, A Siemens Business
 Authors: Ajay Thadhlani - Barefoot Networks
Bhrugurajsinh Chudasama - Barefoot Networks
Kurt Takara - Mentor, A Siemens Business
Gargi Sharma - Mentor, A Siemens Business
9.4FPGA-based Clock Domain Crossing Validation for Safety-critical Designs
FPGA-based Clock Domain Crossing Validation for Safety-Critical Designs Safety and Mission-Critical designs require completeness in Clock Domain Crossing (CDC) verification. However, current verification methods still do not guarantee functional completeness. The paper describes the FPGA-based CDC verification method. It complements existing methods, increasing CDC verification coverage. In this method, synchronizer components include pessimistic model of clock domain crossing effect. It allows designers to verify more synchronization delays combinations, making sure there is no impact on design functionality. Also, synthesizable CDC functional checkers introduced to the design for fast debug of clock domain crossing issues.
 Speaker: Alexander Gnusin - Aldec, Inc.
 Author: Alexander Gnusin - Aldec, Inc.