March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
THURSDAY February 28, 1:00pm - 2:30pm | Pine
KEYWORD: PORTABLE STIMULUS
EVENT TYPE: SHORT WORKSHOP
SESSION 9SW
Using Portable Stimulus to Verify an ARMv8 Sub-System Integration on an SoC

Speakers:
Adnan Hamid - Breker Verification Systems, Inc.
Mike Baird - Willamette HDL
Organizer:
David Kelf - Breker Verification Systems, Inc.
Presenters Mike Baird Founder and President Willamette HDL Adnan Hamid Founder and CEO Breker Verification Systems Abstract The new Accellera Portable Stimulus Standard (PSS) is now being used on the toughest verification problems, particularly at the System-on-Chip (SoC) level. The integration of a multicore ARMv8 sub-system onto an SoC is typical of these challenges, and the use of Portable Stimulus has greatly improved the effectiveness and efficiency of this task on many designs. For engineers working on SoCs and interested to see what other teams are doing to verify these platforms, this workshop is for you. When building a new SoC platform, or placing new IP onto an existing SoC platform there are a number of areas that must be fully verified. The most significant is a check on Cache Coherency, particularly when the platform makes use of three cache levels leveraged by multiple processors and other components across a high-speed fabric. In addition, memory allocation issues, interrupt mechanisms and other ARM integration factors need to be tested. Using Portable Stimulus the majority of this task can be automated, and 100s of tests generated that produce a high coverage result, exercising many complex corner cases. Using content from Willamette’s new Portable Stimulus Training Course, the workshop will commence with an overview of key Portable Stimulus constructs and the concept of how these are used for general SoC verification. This will include small examples of verification scenarios and how these are developed using the new standard. The workshop will then dive into detail on ARMv8 integration verification, including the verification of: cache state transitions, cache line sharing conditions, snoop/probe sources, load/store operation sizes and sources, false sharing cases under concurrent tests, cross cache line boundaries across multiple memory regions, capacity eviction cases, memory ordering tests, all load/store variants, randomized interrupt testing, randomized exception level switching, randomized WFE sleep/wakeup, and general workload testing. We will show how all these tests may be interleaved and operate concurrently to maximize the probability of hitting complex, corner case scenarios.

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