March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

THURSDAY March 05, 1:00pm - 2:30pm | Monterey/Carmel
KEYWORD: HARDWARE/SOFTWARE CO-DEVELOPMENT
EVENT TYPE: SHORT WORKSHOP

SESSION 10SW
SystemRDL to PSS Basic to Pro

Speakers:
Anupam Bakshi - Agnisys, Inc.
Ms. Amanjyot Kaur - Agnisys, Inc.
Organizer:
Neena Chandawale - Agnisys, Inc.

With the growing role of software on the SoCs/IPs of today, the need for a verified Hardware-Software Interface (HSI) which can be leveraged across all teams such as software, RTL front-end, verification, etc., becomes a necessity. Software and hardware engineers alike are asking the questions:

  • Is this the latest version of the RTL code for the register block?
  • This test is running in software. So why is it failing in hardware?
  • Do you have ‘C’ based tests to validate the silicon?
  • Why is your register block having CDC issues?
 

To avoid these issues, design managers and developers alike are now realizing the need to specify the HSI at a higher level of abstraction to define the different types of registers, memory maps, which can automatically generate an “executable”, such as Verilog, VHDL languages, C header files to be leveraged by all the stakeholders involved in the development of the SoC. But with increased complexity of the HSI and the need for different types of special registers, it becomes necessary to create a common verification suite which can be used to verify the HSI by all teams and across different platforms. Relying on manual verification reports from different teams can be unreliable as a number of companies have discovered, when the cause of re-spins has been found to be an issue with a register defined as part of the HSI.

Attend this workshop where you will learn a methodology to easily define the HSI using SystemRDL and generate the desired code for the different teams. SystemRDL, an Accellera standard has been steadily gaining traction and is now being adopted by a number of companies. You will also learn how to develop a golden verification suite which can be leveraged by different teams such as software, firmware, verification teams for different platforms such as simulation, FPGA or silicon. Attendees will also learn how to leverage these custom implementation sequences to create high level test scenarios in PSS to ensure the same sequences are being used by the different teams across the different platforms, thereby accelerating the verification cycle.

Benefits Include:

  • Tutorial on SystemRDL including version 2.0 and its benefits
  • Modeling different types of registers using SystemRDL
  • Generating the different types of outputs such as RTL code, System C, C headers and documentation from a golden specification and customized to your requirements
  • Generating UVM based verification environment and standard tests to verify the HSI
  • Creating custom sequences as building blocks for the high level test scenarios defined in PSS

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