March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY March 04, 3:00pm - 4:30pm | Fir
EVENT TYPE: REGULAR SESSION

SESSION 12
SystemVerilog Solutions
Chair:
Paul Marriott - Verilab, Inc.
Co-Chair:
Mitchell Poplingher - Lockheed Martin Corp.
Verification solutions focusing on the SystemVerilog language.

12.1SystemVerilog Constraints: Appreciating What You Forgot in Class to Get Better Results
Constrained Random Verification automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is your code executes exactly the way it is written and has no concern for what you were thinking. This paper looks at two of the most common issues when results do not match your intent: Verilog expression evaluation, and statistics. It presents a background defining how the SystemVerilog constraint mechanism works, and how these issues play into getting bad results. Finally, it offers a few coding recommendations for improving your code.
 Speaker: Dave Rich - Mentor, A Siemens Business
 Author: Dave Rich - Mentor, A Siemens Business
12.2SystemVerilog Configurations and Tool Flow Using SCons (An Improved Make)
This paper will focus on two types of configurations: SystemVerilog configurations, and SCons. The first part of this paper will address SystemVerilog configurations and how to apply them using the main simulators in the industry. The authors have found the usage model for using configurations with the different simulator tools to be far more complicated than anticipated. The second part of this paper will show how to use SCons to configure and manage design and verification files. SCons is a modern tool that replaces Make.
 Speaker: Don Mills - Microchip Technology Inc.
 Authors: Don Mills - Microchip Technology Inc.
Dillan Mills - Microchip Technology Inc.
12.3*A SystemVerilog Framework for Efficient Randomization of Images With Complex Inter-Pixel Dependencies
Verifying image processing blocks using constrained random verification involves constraining image data to exercise all relevant corner cases. For some types of algorithms, constraining individual pixels is enough. Other algorithms, which operate on blocks, may require complex dependencies among groups of pixels. Expressing such dependencies as constraints on individual pixels is cumbersome and usually places a huge burden on the constraint solver. To address this problem, we have developed a UVM-based SystemVerilog framework that supports the efficient randomization of images with complex interpixel dependencies. This framework has successfully been applied to close coverage for several of our image processing blocks.
 Speaker: Gabriel Jönsson - Axis Communications AB
 Authors: Axel Voss - Axis Communications AB
Gabriel Jönsson - Axis Communications AB
Lars Viklund - Axis Communications AB


* Indicates Best Paper Candidate