WEDNESDAY March 04, 8:30am - 9:30am | Oak/Fir
DVCon attendees are invited to attend a Town Hall discussion on the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V.
Chip design verification engineering can expect any number of disruptions caused by the slowdown of Moore’s law and the breakdown of the von Neumann architecture. At the least, expect to see bigger, more powerful devices for high-performance computing, artificial intelligence, and automotive electronics applications coupled with the move toward open-source development efforts, and architectural changes such as processing-in-memory. Complex chips and systems require formidable, robust verification methodologies that augment traditional simulation-based verification, hardware emulation, and formal verification that won’t match their demands. Vagaries of open-source design including extended RISC-V general processor instruction sets and in-memory processing further drive the new paradigm.
Technology Editor Brian Bailey from Semiconductor Engineering will lead a discussion with panelists and attendees about the needs of the future. They will attempt to address whether a new verification methodology to support these widely differing scenarios will cause an upheaval in the well-ordered verification flow. The panel will review a variety of new ideas, including the continuum of verification engines, the intelligent abstract testbench, cloud-based execution solutions, the merging of hardware and software and the expanding role of verification into safety, security and more.
This session could represent a pivotal moment where attendees voice next-generation verification requirements addressed by panelists and other participants in a town hall-like setting.