March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

WEDNESDAY March 04, 3:00pm - 4:30pm | Monterey/Carmel
EVENT TYPE: REGULAR SESSION

SESSION 13
Reset Domain Challenges
Chair:
Kamel Belhous - Teradyne, Inc.
Verification challenges focusing on reset domain crossings.

13.1Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Today, in automotive circuits, as electronic systems are increasingly replacing mechanical systems, the concerns to make system fail-safe have increased. However, as with all electronics, things can go wrong sometimes, hardware can fail. Modern automotive Systems on Chips (SoCs) typically contain multiple asynchronous reset signals to ensure systematic functional recovery from such unexpected situations and faults. The complex reset architecture leads to a new set of problems such as reset domain crossings (RDCs). In this paper, we present a systematic methodology to identify critical reset domain bugs and solve them to ensure a high degree of quality in automotive SoCs.
 Speaker: Anwesha Choudhary - Mentor Graphics (India) Pvt. Ltd.
 Authors: Akanksha Gupta - Mentor Graphics (India) Pvt. Ltd.
Anwesha Choudhary - Mentor Graphics (India) Pvt. Ltd.
Ankush Sethi - NXP Semiconductors
Kurt Takara - Mentor, A Siemens Business
Kriti Garg - NXP Semiconductors
Aniruddha Gupta - NXP Semiconductors
13.2Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
With the increasing complexity of designs, reset architecture is becoming complex making RDC verification a critical step in verification. As design size increases, flat RDC verification on SoC becomes infeasible. There is a need for a distributed RDC verification mechanism, where each module can be verified separately and then integrated for complete verification. The primary challenge for distributed methodology is to understand the reset architecture of complete SoC. We present a Hierarchical RDC verification approach that is complete and accurate. The proposed approach is based on a data model, which captures RDC intent of IP allowing seamless integration wherever the IP is reused.
 Speaker: Kurt Takara - Mentor, A Siemens Business
 Authors: Soumya Palit - Mentor, A Siemens Business
Anwesha Choudhury - Mentor, A Siemens Business
Kurt Takara - Mentor, A Siemens Business
13.3Innovative Techniques to Solve Complex RDC Challenges
Traditionally, reset design and verification are done by design engineers’ and they are expected to follow some standard reset architecture guidelines to avoid any potential meta-stability issues. However, with the advent of complex power management design flows and with the increase in reset signaling complexity across multiple reset domains, reset domain crossing verification becomes an absolute need to ensure glitch-free reset assertions during various power states. This paper details about complex RDC challenges and the methodology in the PCIE Subsystem and proposed two simple techniques- RDC bridge & STA based RDC to solve such challenges.
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd.
 Author: Rohit K. Sinha - Intel Technology India Pvt. Ltd.