TUESDAY March 03, 9:00am - 10:30am | Fir
EVENT TYPE: REGULAR SESSION
Tom Fitzpatrick - Mentor, A Siemens Business
Vibarajan Viswanathan - Samsung Austin R&D Center
Practical applications using the new Portable Test and Stimulus Standard.
|2.1||ISO 26262 Dependent Failure Analysis Using PSS|
|Dependent Failure Analysis (DFA) is a methodology defined in ISO-26262 to analyze the impact of errors on one shared resource to other elements and find safety vulnerabilities. Coherency is a good example of resource sharing and is thus critical for failure analysis. The reusability and constrained-random generation provided by the Portable Test and Stimulus Standard (PSS) and tools helped to generate the Dependent Failure Initiator (DFI) for the DFA. In this paper, we discuss how PSS and tools are used to inject faults and generate interference stimulus to verify the safety mechanism against dependent failures.|
|Speaker:||Moonki Jang - Samsung Electronics Co., Ltd.
|Authors:||Moonki Jang - Samsung Electronics Co., Ltd.
Jiwoong Kim - Samsung Electronics Co., Ltd.
Dongjoo Kim - Samsung Electronics Co., Ltd.
Shai Fuss - Cadence Design Systems, Inc.
Zeev Kirshenbaum - Cadence Design Systems, Inc.
|2.2||Designing PSS Environment Integration for Maximum Reuse|
|The Accellera PSS language standard enables users to capture a model of test intent that is portable across verification levels and execution platforms. Challenges in reusing the integration between the PSS model and the environment severely impacts the overall reuse benefits of applying PSS. This paper highlights the challenges in productively integrating PSS with the environment, and covers key criteria for a PSS/environment integration that maximizes the reuse of both the environmental elements and the PSS description. It describes key elements of a framework that maximizes PSS and test realization reuse across UVM-based testbench environments, and between UVM and embedded-software environments.|
|Speaker:||Matthew Ballance - Mentor, A Siemens Business
|Author:||Matthew Ballance - Mentor, A Siemens Business
|2.3||Post-Silicon Performance Validation Using PSS|
|We will discuss the challenge of verifying multiple versions of our test chip, and how we used the Portable Test and Stimulus Standard (PSS) in addressing this challenge. Our test chip contains 5 CPU blocks, implemented using different design methodologies. One goal of our test chip is to evaluate the performance and power consumption of targeted design methodology. Using PSS and Perspec, we created re-usable test scenarios and let the tools handle the randomization, resource allocation, synchronization, and actual C code generation. By this approach, TAT for software environment setup is reduced and the quality of performance testing is improved.|
|Speaker:||Dayoung Kim - Samsung Electronics Co., Ltd.
|Authors:||Dayoung Kim - Samsung Electronics Co., Ltd.
Jaehun Lee - Samsung Electronics Co., Ltd.
Daeseo Cha - Samsung Electronics Co., Ltd.
Phu Huynh - Cadence Design Systems, Inc.
Jake Kim - Cadence Design Systems, Inc.