March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
MONDAY March 02, 1:45pm - 3:15pm | Fir
KEYWORD: PORTABLE STIMULUS
EVENT TYPE: SHORT WORKSHOP
SESSION 2SW
Dealing with Programmable IP: Where the Rubber Meets the PSS Deployment Road
Speaker:
Karthick Gururaj - Vayavya Labs Pvt., Ltd.

Technologies and tools based on Portable Test and Stimulus Standard (PSS) are being embraced by the verification teams for the enormous value it brings about: from being able to reason about verification intent in the abstract level - to the productivity boost with automatic generation of test-cases.

One of the major challenges that verification engineers face in deploying PSS tools is managing programmable peripheral devices during the test-case execution. For example, the bare-metal C software drivers that are needed for system-level verification are today implemented manually - for both internal and 3rd party IP. This is an effort-intensive and error-prone work. Additionally, verification use-cases that involve complex I/O devices (like PCIe controller) require significant software content.

Using Hardware/Software Interface (HSI) based automation in your verification flow offers immediate and substantial benefits. The use of automation cuts downtime in developing device drivers, improves quality, and promotes reuse of the stimulus model. The proposed inclusion of HSI constructs in the next version of PSS standard will enable an exchange of programmable specification of peripheral IP between IP supplier and IP users - allowing verification teams to easily create device drivers for their environment. The use of HSI also promotes the creation of reusable software stacks for I/O that can “shift-left” your verification schedule. For example, the software stack for a PCIe controller can perform operations like enumeration, handling MSI/MSI-X interrupts, etc.

This tutorial offers an in-depth view of Hardware/Software Interface (HSI) specification, software stacks, and application to verification of a typical SoC. Following topics will be covered in the tutorial:

  • Using HSI in deployment of PSS based tools for your SoC design
  • Verification scenarios involving complex I/O
  • Best practices for creating reusable PSS models

The tutorial will include examples drawn from real-life projects - and is intended for system-level verification engineers, verification architects, firmware engineers, and peripheral IP development teams. All the topics above will include code examples. Familiarity with PSS1.0 specification will be helpful, but not mandatory.

About the Speaker:

Karthick is a Principal Architect at Vayavya Labs. He has about 20 years of industry experience in SystemC modeling, virtual platforms, and device drivers. He started his career with NXP Semiconductors where he led several standardization activities as a part of the NXP's CoReUse program. He has represented NXP in OSCI-TLM workgroup (now part of Accellera consortium) and contributed to SystemC TLM2.0 standard. The virtual prototyping activities at NXP introduced him to the diverse market segments of Home consumer, Car infotainment, Mobile and Identification.

At Vayavya Labs, Karthick is part of the DDGen product team - the industry's only comprehensive tool for HSI specification. He is an active contributor in Accellera's Portable Stimulus Work Group and has several patents in the domain of hardware/software interfacing and its applications.


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