March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

THURSDAY March 05, 8:30am - 11:30am | Cascade
KEYWORD: VERIFICATION PRODUCTIVITY METHODS
EVENT TYPE: TUTORIAL

SESSION 2T
Next Generation Verification for the Era of AI/ML and 5G

Speakers:
Frank Schirrmeister - Cadence Design Systems, Inc.
Larry Melling - Cadence Design Systems, Inc.
Amit Dua - Cadence Design Systems, Inc.
Moshik Rubin - Cadence Design Systems, Inc.
Pete Hardee - Cadence Design Systems, Inc.
Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc.
Artificial intelligence, machine learning, and next-generation 5G networking are changing consumer’s day-to-day lives at breathtaking speeds and are driving a new wave of chip design starts that pose new requirements for verification driven by the complexity of designs and applications. To keep up with the ever-growing need to improve productivity, EDA itself also is applying AI and ML techniques to the design process itself as well. This tutorial will analyze the requirements of AI, ML, and 5G applications and their impact on the chip verification and software development process, as well as introduce innovative enabling data-driven verification that goes beyond metrics towards efficiency. This tutorial will also introduce how AI/ML are increasing verification productivity in the formal, simulation, emulation, prototyping, debug, VIP, and test automation domains.

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