TUESDAY March 03, 9:00am - 10:30am | Monterey/Carmel
EVENT TYPE: REGULAR SESSION
Dave Rich - Mentor, A Siemens Business
Loganath Ramachandran - Accelver Systems Inc.
Techniques to add automation into verification processes.
|3.1||Machine Learning-Guided Stimulus Generation for Functional Verification|
|Machine learning techniques have been explored to reduce chip functional verification time, which is a well-known bottleneck for product time to market. In this work, various recently popular machine learning techniques are studied for accelerating functional verification coverage. The study covers different granularity levels of machine learning applications, Finite State Machine (FSM) and non-FSM designs. Experimental results show that our techniques can reduce overall verification time by around 70% even when the machine learning model training time is counted.|
|Speaker:||Jiang Hu - Texas A&M Univ.
|Authors:||Saumil P. Gogri - Texas A&M Univ.
Jiang Hu - Texas A&M Univ.
Aakash Tyagi - Texas A&M Univ.
Michael D. Quinn - Texas A&M Univ.
Swati Ramachandran - Texas A&M Univ. & Arm, Ltd.
Fazia Batool - Texas A&M Univ.
Amrutha Jagadeesh - Texas A&M Univ.
|3.2||Automated Generation of RAL Based UVM Sequences|
|A specific ordering of register programming is often defined by architects to describe how to configure features within a design. These get translated to uvm_sequences on the testbench side that can take advantage of a RAL (Register Abstraction Layer). Features constantly undergo modifications in projects under development, and subsequently, a lot of validators will need to manually keep sequences in their testbenches up-to-date. This paper proposes a way of automating the generation of these uvm_sequences of a DUT(device under test) using a machine-readable master spec.|
|Speaker:||Satyajit J. Sinari - Intel Corp.
|Authors:||Vijayakrishnan Rousseau - Intel Corp.
Benjamin T. Applequist - Intel Corp.
Geddy Lallathin - Intel Corp.
Satyajit J. Sinari - Intel Corp.
Timothy A. McLean - Intel Corp.
|3.3||Accelerating SoC Verification Using Process Automation and Integration|
|Our approaches are to combine cross-disciplinary workflows together, automate their execution, explore design or verification results, and identify design or verification issues subject to required criteria. The system is able to manipulate and configure parametric input/output data between process steps and automates multiple simulations/emulations to greatly improve efficiency, reduce manual errors, and accelerate product designs.|
|Speaker:||Seonghee Yim - Samsung Electronics Co., Ltd.
|Authors:||Seonghee Yim - Samsung Electronics Co., Ltd.
Hanna Jang - Samsung Electronics Co., Ltd.
Sunchang Choi - Samsung Electronics Co., Ltd.
Seonil Choi - Samsung Electronics Co., Ltd.