March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.
MONDAY March 02, 1:45pm - 3:15pm | Monterey/Carmel
System Level Flows for SoC Architecture Analysis and Design
Swaminathan Ramachandran - CircuitSutra Technologies Pvt. Ltd.
Umesh Sisodia - CircuitSutra Technologies Pvt. Ltd.

As SystemC gains popularity in the fields of architecture evaluation, virtual platform development, SoC-level verification, etc., more teams and companies want to explore, experiment and deploy it for their modeling use cases. While the SystemC library provides the vocabulary and the nuts and bolts to build a useful and diverse set of models, it is sometimes too low-level to be immediately useful.

What is needed is a SystemC library analogous to Boost libraries in C++, for building blocks like memories, buses, registers, timers, etc. along with the infrastructure to quickly stitch them together into a working platform asap. Most of the Semiconductor companies who have successfully deployed SystemC, have developed their own tool independent methodology on top of SystemC, and they use it together with advanced modeling tools from EDA vendors. Such a library usually starts with basic building blocks, and over a period of time becomes a very rich collection of re-usable modeling components that can be re-used across various IP models, SoC variants, Modeling use cases, Business units, etc. Any company looking to adopt SystemC in their flows should carefully conceptualize the development of such a methodology in-house and can learn from the best practices being followed in the industry.

In this presentation, we will talk about what should be the content of such a methodology/library and how it should be conceptualized. CircuitSutra has worked with leading semiconductor companies for more than a decade now and has participated in modeling projects from the stage of experimentation to pilot projects and to widespread adoption. We have an in-depth understanding of the best practices followed in the modeling domain.

High-Level Synthesis (HLS) raises the abstraction of chip design beyond RTL. It enables the implementation of design functionality in high-level languages like C++/SystemC and generates corresponding RTL using HLS tools. Synthesizable C++/SystemC code for a design is very concise as compared to equivalent RTL code for the same design. Moreover, simulation of C++/SystemC models is much faster compared to RTL simulation. This allows significant productivity gains in the design and verification process. HLS also allows separation of functionality from architecture constraints and technology parameters, thus permitting code re-use across different variants of semiconductor chips, or across FPGA and ASICs.

HLS flows are more effective for algorithm-centric designs. Nowadays, we see new chip design requirements for emerging domains like 5G, deep learning, vision, image processing, speech, audio processing, etc. In these domains, there are many algorithms implemented in software and several of these are available as open source.

In this talk, we will present an HLS-based methodology to quickly migrate a software algorithm implemented in plain C/C++ to a hardware implementation in RTL for semiconductor chips (FPGA or ASIC). We will also cover a verification flow that allows the reuse of the original test suite of the software algorithm to verify the synthesizable C++/SystemC model as well as the final RTL. The untimed C++/SystemC models are also suitable to be used in Virtual Platforms, that allows embedded software development much before the chip is designed.

This methodology accelerates the pace of innovation, enables faster rollout of new chips, permits experimentation by quickly trying out the functionality in software and hardware, and taking high-level architecture decisions much earlier in the cycle.

SystemC is a C++ library created for design and verification at SoC and system level. It is widely used in the industry for system-level modeling, virtual prototyping, hardware-software co-verification, architecture & performance modeling, high-level synthesis, and functional verification. RISC-V is an open-source processor ISA. Given that RISC-V ecosystem is in a nascent stage, yet there is widespread interest in the industry to explore the usage of RISC-V for various use cases. A robust modeling eco-system is necessary for the successful adoption of a new ISA, and in this context, a need exists for SystemC modeling infrastructure for RISC-V ecosystem. In this presentation, we will talk about some essential components required for anyone trying to deploy SystemC based methodologies for their RISC-V project.

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