March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY March 03, 10:30am - 12:00pm | Gateway Foyer

Poster Session
John Dickol - Samsung Austin R&D Center
Erik Seligman - Intel Corp.
Kaiming Ho - Independent
Dave Rich - Mentor, A Siemens Business
Paul Marriott - Verilab, Inc.
Mitchell Poplingher - Lockheed Martin Corp.
Progyna Khondkar - Mentor, A Siemens Business
Phu Huynh - Cadence Design Systems, Inc.
Kelly Larson - Tesla Motors, Inc.
Josh Rensch - Semifore, Inc.
Stephen D'Onofrio - Paradigm Works, Inc.
Kamran Haqqani - Maxim Integrated
Nagi Naganathan - Northrop Grumman Corp.
Ning Guo - Advanced Micro Devices, Inc.

4.1SoC Firmware Debugging Tracer in Emulation Platform
An efficient SoC firmware performance analysis mechanism using tracer fine-tuned to emulation platform. HW-SW coverification in multicore environment is a big challenge. Currently we have lot of firmware solutions,that are costly and not compatible with all platforms. ForExample, existing debuggers will have breakpoint feature that will not exactly captures dynamics of the system due to limitation and have difficulty in exact reproduction of bugs or fixing the issue. Also SW debuggers only depict the behavior of the software, but not together with hardware. This novel approach captures the FW-HW states and enable developers to optimize for getting maximum performance.
 Speaker: Kubendra Kumbar - Samsung Semiconductor India R&D, Bangalore
 Authors: Kubendra Kumbar - Samsung Semiconductor India R&D, Bangalore
Sandeep Vallabhaneni - Samsung Electronics Co., Ltd.
Ken Joseph Kannampuzha - Samsung Semiconductor India R&D, Bangalore
Shim Hojun - Samsung Electronics Co., Ltd.
Byung C. Yoo - Samsung Electronics Co., Ltd.
4.2IDeALS for All - Intelligent Detection and Accurate Localization of Stalls
In any complex pipelined system that consists of several blocks, it is possible to encounter functional issues that block forward progress in the system. These can arise out of either Deadlock or Livelock scenarios. These can be extremely challenging to debug or root cause in a post-silicon environment. It is therefore highly desirable to detect all such defects in a pre-silicon environment. There could concurrently be several defects in one or many RTL blocks, hence the additional need for localization. In this paper, we present a method to intelligently detect and accurately localize stalls caused by deadlocks and livelocks (IDeALS).
 Speaker: Pallavi Jesrani - Advanced Micro Devices, Inc.
 Author: Pallavi Jesrani - Advanced Micro Devices, Inc.
4.3Covergate: Coverage Exposed
Coverage is widely used and deployed. But it is still the realm of the specialist or the Verification IP. This paper will explore and simplify coverage through examples and use models. It will explore functional coverage, line coverage, expression coverage among others. It will explore coverage debug and coverage distribution. The examples offer a guide for simple, easy to use coverage models.
 Speaker: Rich Edelman - Mentor, A Siemens Business
 Author: Rich Edelman - Mentor, A Siemens Business
4.4Increasing Regression Efficiency with Portable Stimulus
Functional coverage closure using random testing of modern complex designs is a tough task. Closure of last few hundreds of bins (1% to 2%) require manual effort, which is the most difficult part of the entire procedure. This pa-per explains the experience and results of deploying a portable stimulus-based verification methodology to boost regression efficiency for an existing System Verilog test bench, reduce required manual intervention, and enable closing functional coverage in a short and predictable time
 Speaker: Niyaz K. Zubair - Qualcomm India Pvt. Ltd.
 Authors: Niyaz K. Zubair - Qualcomm India Pvt. Ltd.
Kota Subba Rao Sajja - Qualcomm India Pvt. Ltd.
4.5RegAnalyzer - A Tool for Programming Analysis and Debug for Verification and Validation
As the technology node is shrinking, more and more IPs are getting integrated in single System-on-chip. In the System-on-chip, verification is getting to be a more tedious, time-consuming and challenging task. Based on a case study on different internal and third-party IPs, it is realized that there are no mechanisms nor internal/external tools available for doing the quick debug by understanding the test cases. Verification Engineers are putting manual effort to understand the IP programming in the test cases and there is no direct way to map the register programming to the Technical Reference Manual / Programmers model. RegAnalyzer tool is to resolve this.
 Speaker: Suresh Vasu - Intel Technology India Pvt. Ltd.
 Author: Suresh Vasu - Intel Technology India Pvt. Ltd.
4.6Key Gochas in Implementing CDC for Various Bus Protocols
When multiple clock domains exist, complications occur, such as setup and hold time differences which leads to metastability state. Other issues include violation of the bus protocols. The 2-D flip flop technique only solves the CDC issues for 1-bit transaction. Automation has been done for the generation of design and verification code from the specification for multi-bit transactions eliminating all the CDC related issues for various bus protocols. The full paper will talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.
 Speaker: Neena Chandawale - Agnisys, Inc.
 Authors: Nikita Gulliya - Agnisys, Inc.
Mukesh Kumar Singh - Agnisys, Inc.
Abhishek Bora - Agnisys, Inc.
4.7Multimedia IP DMA Verification Platform
Usually, DMA verification had to be done by senior verification engineer because even a small bus protocol can hang up the BUS of the whole SoC. In this paper, we introduce a multimedia IP DMA verification platform that could be easily used by verification beginners and could accumulate DMA verification know-how of experienced engineers to this platform. Through this platform, we were enabled to make a new DMA testbench within 30 minutes, even if novice verification engineers were completing the work, we could verify several DMA instances at the same time with enough verification quality.
 Speaker: Suhyung Kim - Samsung Electronics Co., Ltd.
 Authors: Suhyung Kim - Samsung Electronics Co., Ltd.
Sangkyu Park - Samsung Electronics Co., Ltd.
Myungwoo Seo - Samsung Electronics Co., Ltd.
Sangjin Lee - Samsung Electronics Co., Ltd.
Jiyeon Park - Samsung Electronics Co., Ltd.
4.8How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros
The integration of macros with low power designs and conduct power aware (PA) verification are always complex and cumbersome. This paper distinctively studies the inherent integration features of soft & hard macros that are inevitable for low power designs. This has been done by thoroughly identifying the semantic gaps between physical interpretations of macros with their low power orientations. We will address challenges between hierarchical back end flows to flat front-end simulation flow. The motivation is to create a complete low power integration and verification solution for soft & hard macros.
 Speaker: Progyna Khondkar - Mentor, A Siemens Business
 Authors: Madhusudhana Lebaka - Qualcomm Technologies, Inc.
Abraham Guizer - Mentor, A Siemens Business
Progyna Khondkar - Mentor, A Siemens Business
4.9Advantages of Using UVM/System Verilog IEEE Standards to Verify Complex Probabilistic Constellation Shaping Design for a Coherent DSP ASIC
This paper demonstrates the advantages provided by UVM/SystemVerilog IEEE-standards to verify a complex Probabilistic Constellation Shaping[PCS] Algorithm in a high-performance Coherent-DSP ASIC. The goal was to maximize the reuse of environment components, leveraging all the base and extended sequences. Testbench integrated hundreds of instances of Encoders and Decoders working in parallel, created a layered verification environment topology that mirrored the design hierarchy. To achieve this, we used transaction-level modeling, and integration of C-reference models as part of UVM-components, making them reusable at each layer of integration. This resulted in seamless integration and adaptability of environments via different high-level configurations.
 Speaker: Nipun G. Bhatt - Infinera Corp.
 Author: Nipun G. Bhatt - Infinera Corp.
4.10“Shift Left” Hierarchical Low-Power Static Verification Using SAM
With increasing SoC complexity, growing design sizes and advanced power-aware architectures, early and efficient static low power verification is important to reduce turnaround times and enable faster time to market. For hierarchical verification, designers use a black box flow, liberty model-based hierarchical flow, ETM flow or a glass box flow that offers various degrees of trade-offs between accuracy and performance. Signoff Abstract Models (SAM) is designed to provide the same QoR and achieves better performance than flat runs. The paper showcases this methodology and results that can be achieved with a “shift-left” in overall low power static verification signoff.
 Speaker: Himanshu Bhatt - Synopsys, Inc.
 Authors: Himanshu Bhatt - Synopsys, Inc.
Parag Mandrekar - Advanced Micro Devices, Inc.
Bharani Ellore - Advanced Micro Devices, Inc.
Susantha Wijesekara - Synopsys, Inc.
Bhaskar Pal - Synopsys India Pvt. Ltd.
4.11Are You Safe Yet? Safety Mechanism Insertion and Validation
As functional safety becomes increasingly important in today's industrial and automotive designs, a lot of legacy designs have to be “upgraded” to meet the safety goal of the system. An efficient approach is to use safety synthesis and formal verification to incorporate a safety architecture into the design. The flow can consist of these major steps: 1) identify areas of the design where better fault detections are required, 2) introduce the right safety mechanisms into the design with safety synthesis, 3) validate the design changes with formal verification, and 4) perform formal fault injection to measure the diagnostic coverage.
 Speaker: Ping Yeung - Mentor, A Siemens Business
 Authors: Ping Yeung - Mentor, A Siemens Business
Jin Hou - Mentor, A Siemens Business
Vinayak Desai - Mentor, A Siemens Business
Jacob Wiltgen - Mentor, A Siemens Business
4.12Saving and Restoring Simulation Using UVM Factory Overriding to Reduce Simulation Turn Around Time
This paper proposes Save and Restore Methodology which contributes to shortening simulation turn-around-time. The main purpose of Save and Restore Methodology is to save the simulation execution time that is for an identical portion, such as booting sequence, in all test scenarios, by saving a snapshot of simulation result at the end of identical portion and restoring that snapshot for all test scenario simulation. The solution is to override UVM sequences using a UVM Factory Override Mechanism. In this study, we show how to achieve UVM sequence override, followed by the advantages of Save and Restore methodology.
 Speaker: Ahhyung Shin - Samsung Electronics Co., Ltd.
 Authors: Ahhyung Shin - Samsung Electronics Co., Ltd.
Yungi Um - Samsung Electronics Co., Ltd.
Youngsik Kim - Samsung Electronics Co., Ltd.
Brian Choi - Samsung Electronics Co., Ltd.
4.13Integration of HDL Logic Inside SystemVerilog UVM-Based Verification IP
The level of complexity of the Verification IPs which need to be developed during the verification process is dictated by the complexity of the system that is surrounding the Device under Test. This paper will propose the method of the integration of HDL Design Logic inside a VIP Wrapper which would simplify the process of VIP development and increase the precision with which VIP will model expected Design behavior. It will discuss use-cases for this method as well as its advantages and disadvantages.
 Speaker: Aleksandra M. Panajotu - Elsys Eastern Europe d.o.o.
 Author: Aleksandra M. Panajotu - Elsys Eastern Europe d.o.o.
4.14Deadlock Verification For Dummies - The Easy Way Using SVA and Formal
System deadlock or lockup is notoriously difficult to detect with RTL simulations. However, exhaustive formal-based analysis is uniquely qualified to deliver results in this domain. Deadlock properties have been extensively studied and can be precisely specified using mathematical languages such as LTL and CTL. Unfortunately, LTL and CTL are academic languages, and as such are cumbersome and lack support in industrial verification tools. Assertion languages have the concepts of safety and liveness properties which lack the same semantics as the academic languages. This paper discusses new automation in leveraging SVA properties to verify and debug deadlock in RTL designs.
 Speaker: Mark Eslinger - Mentor, A Siemens Business
 Authors: Mark Eslinger - Mentor, A Siemens Business
Jeremy Levitt - Mentor, A Siemens Business
Joe Hupcey III - Mentor, A Siemens Business
4.15Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros
Today there are limited ways that supply connections to multi-rail can be described in an abstract, generic manner—leading to the verbose and tedious practice of explicitly specifying supply set connections within UPF files. Rather than simply including a sub-component macro within the appropriate power domain, supply net connections must be made directly to the macro supply ports. This paper proposes enhancements to the UPF standard and extensions to the Liberty model format that would allow multi-rail modules to benefit from the same automatic supply set connections based on power domain membership that connect standard cells today.
 Speaker: Brandon Skaggs - Cypress Semiconductor Corp.
 Author: Brandon Skaggs - Cypress Semiconductor Corp.
4.16Automated RTL Update for Abutted Design
The most important factors to be considered for SoC chip design are performance, power, and area. Among them, the absolute factor related to the cost of chip manufacture is the area. New technologies to reduce chip area are being continuously researched. One of the various technologies to reduce chip area is to design an abutted floorplan. Abutted floorplan can reduce area by eliminating top-level routing area in the chip. For abutted design, RTL should be updated for reflecting design modification requested by physical designers, without error, in a short time. This paper introduces the RTL update automation methodology for abutted design.
 Speaker: Wonkyung Lee - Samsung Electronics Co., Ltd.
 Authors: Wonkyung Lee - Samsung Electronics Co., Ltd.
Ayoung Kwon - Samsung Electronics Co., Ltd.
Soyeong Kwon - Samsung Electronics Co., Ltd.
Youngsik Kim - Samsung Electronics Co., Ltd.
Seonil Brian Choi - Samsung Electronics Co., Ltd.
4.17Efficient Methods for Display Power Estimation and Visualization
As power is becoming more prominent in the graphics domain, it is critical to estimate power to meet average and peak power budgets in the pre-silicon environment. Typically, power in Intel Display IP is calculated using RTL simulations based on toggling of all logic in the design. This approach is useful for single frame tests, however for large frame and high-resolution tests like UHD and 8K, it is impractical to scale this approach and would take 1-2 weeks slowing down the entire process. This paper discusses a methodology to solve the problem using emulation instead to get a speedup of 7-14x in generating waveforms.
 Speaker: Srikanth Reddy Rolla - Intel Corp.
 Authors: Srikanth Reddy Rolla - Intel Corp.
Aakash K. Modi - Intel Corp.
4.18Use of Aliasing in SystemVerilog Verification Environment
This paper introduces aliasing techniques when designing a SystemVerilog verification environment. It presents examples of a UVM environment, in which “alias” can provide a convenient way when building the testbench and help to prevent mistakes. While the SystemVerilog Standard does not define “alias” in the class construct, this paper will start with a discussion on the fundamental theory behind aliasing first, then show how to implement your own “alias” in the codes. Furthermore, it will expand the discussion on various applications and techniques of aliasing in different use cases, as well as the potential limitations in each one of them.
 Speaker: Evean Qin - Advanced Micro Devices, Inc.
 Author: Evean Qin - Advanced Micro Devices, Inc.
4.19Advanced SoC Randomization Tool for Complex SoC-Level Verification
Introduction: With the development of modern SoC design, SoC-level verification becomes more and more complex and time-consuming. One proposal is to develop an advanced SoC Randomization tool, which can automatically generate a random SoC mixed traffic test scenario based on our predefined constraints. In order to accomplish this goal, this tool must 1) provide powerful “constrained random” methods, 2) automatically generate C/ASM based test cases which can dynamically load to an SoC TestBench during simulation, 3) be able to reproduce the same test scenario with the same seed, 4) no needs to recompile SoC TestBench if have to modify/fix test issues.
 Speaker: Xiao Mei - Advanced Micro Devices, Inc.
 Authors: Xiao Mei - Advanced Micro Devices, Inc.
Chris Weller - Advanced Micro Devices, Inc.
Michael Sedmak - Advanced Micro Devices, Inc.
Zhiqiang Ren - Advanced Micro Devices, Inc.
4.20Safety and Security Aware Pre-Silicon Concurrent Software Development and Verification
Simultaneously designing and testing software and SoC designs before silicon is an enticing goal to reduce the time and cost of building embedded devices. The earlier that applications can run on a reliable representation of the SoC, the better. Merging the software and SoC paths before silicon saves time and money and creates a virtuous cycle that gets the embedded product to market faster. This paper describes a new pre-silicon continuum for concurrent SoC and software development and verification for safety and security-critical systems, composed of a safety-certified RTOS and advanced C/C++ development tools that continuously support SoC verification.
 Speaker: Frank Schirrmeister - Cadence Design Systems, Inc. & Vayavya Labs Pvt., Ltd.
 Authors: Frank Schirrmeister - Cadence Design Systems, Inc. & Vayavya Labs Pvt., Ltd.
Joe Fabbre - Green Hills Software, Inc.
Max Hinson - Green Hills Software, Inc.