March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY March 03, 3:00pm - 5:00pm | Oak

UVM Strategies
Srivatsa Vasudevan - Synopsys, Inc.
Neel Sonara - Broadcom Corp.
Tips and tricks to make better use of the Universal Verification Methodology.

5.1*UVM – Stop Hitting Your Brother Coding Guidelines
The UVM standard has promised a perfect world where we all follow a common set of guidelines for testbenches and connect verification IP. Just don’t look too closely at the standard. UVM carries baggage from previous standards such as OVM, VMM, eRM, AVM, and more. This paper describes situations where UVM provides multiple ways to solve a problem, explains the issues with certain approaches, and recommends solutions with warnings.
 Speaker: Chris Spear - Mentor, A Siemens Business
 Authors: Chris Spear - Mentor, A Siemens Business
Rich Edelman - Mentor, A Siemens Business
5.2Multithreading a UVM Testbench for Faster Simulation
A common way to verify results in simulations is to use the UVM to create predictors and scoreboards. One possible implementation of a predictor is to use SystemVerilog DPI calls and have C++ code model the results. This provides a higher level of abstraction and the potential reuse of the software model; however, it can potentially cause performance degradation due to the simulator halting while the software model runs. To greatly increase throughput a C++ thread pool can be introduced to handle the execution of all predictor models, allowing the simulation and predictors to be run in parallel.
 Speaker: Benjamin T. Applequist - Intel Corp.
 Authors: Benjamin T. Applequist - Intel Corp.
Vijayakrishnan Rousseau - Intel Corp.
Andrew Tan - Intel Corp.
Jayasrinivas Sesham - Intel Corp.
5.3*UVM Reactive Stimulus Techniques
UVM reactive stimulus techniques allow sequences to receive feedback from a Design Under Test (DUT) to determine what stimulus should be sent next. Existing documentation and examples describe some of the requirements to create sequences and drivers with both request (REQ) type and response (RSP) type parameters, but the descriptions are somewhat incomplete regarding how to create the response (RSP) transaction that is fed back to the sequence. This paper describes all of the necessary steps to create efficient reactive stimulus sequences. The paper describes how those techniques can be used to test an example of synchronous FIFO design.
 Speakers: Heath Chambers - HMC Design Verification, Inc. & Sunburst Design, Inc.
Clifford E. Cummings - Sunburst Design, Inc.
 Authors: Clifford E. Cummings - Sunburst Design, Inc.
Heath Chambers - HMC Design Verification, Inc. & Sunburst Design, Inc.
Stephen D’Onofrio - Paradigm Works, Inc. & Sunburst Design, Inc.

* Indicates Best Paper Candidate