Paul Marriott - Verilab, Inc.
Jason Sprott - Verilab, Inc.
This short workshop delivers techniques, tricks, skills, and insight for engineers facing the challenges of verifying a highly configurable parameterized design using the Universal Verification Methodology (UVM).
Who will benefit?
To get the most out of this event, attendees should have sound basic knowledge of SystemVerilog and the UVM, and experience of their use on at least one verification project. The workshop will be of greatest value to verification engineers and technical leads who are, or soon will be, working on a project where the RTL device under test (DUT) is highly configurable (parameterized).
Such configurability is commonly found in generic design IP such as bus fabric, memory controllers, and high-speed interfaces. Although the focus is on the UVM, many of the ideas presented will also be of value to those using other verification techniques such as formal property verification.
This tutorial workshop brings together a collection of powerful techniques and good practice learned through experience on many large-scale projects. Drawing on hard-earned wisdom of Verilab’s experienced team, highlights of published papers, and new material created especially for the event, it provides a themed tutorial for engineers working on verification projects testing configurable or parameterized RTL. The workshop’s recommendations, guidance, and examples aim to be immediately useful, and its insights will have continuing value in your future work.
Delegates will be able to download the presentations, with explanatory notes, soon after the event. To add even greater value and to support delegates’ further in-depth reading, a curated and annotated collection of papers written by various Verilab consultants will be available alongside the workshop materials.
Challenges of verifying highly parameterized RTL:
Generic, reusable design elements (blocks or subsystems) must be configurable so that the design can be re-shaped for many different situations without the need to rewrite the design RTL. This configurability is a powerful feature of modern designs, often achieved through a combination of code generation techniques and traditional use of RTL parameters. Current verification methodologies, whether formal or dynamic, can test only a single parameterization in any given run. We will outline the impact of this problem on verification planning and process.
Impact of parameterization on a UVM testbench:
The core of this workshop is a detailed, practical discussion of a range of techniques that allow a single UVM testbench code base to be used for any parameterization of a DUT without laborious, error-prone rewriting. Verilab has wide and deep experience of verifying highly configurable RTL, and we will share our favorite project-proven techniques covering important areas of concern including:
- Creating UVM verification components with configurability in mind
- The UVM Harness approach to simplify RTL hookup to the testbench
- Proper use of the UVM resource or configuration database as a tool for configurability
- Avoiding the many pitfalls associated with propagating RTL parameter values into an object-oriented testbench
- Ensuring that your UVM register model correctly takes account of the effect of RTL parameters on the design’s registers
- Re-shaping functional coverage (covergroups, points, and bins) in response to RTL parameters
- Setting appropriate, measurable verification goals for parameterization, to answer the question “have we verified the required set of configurations?”
- Dealing with design code that is generated rather than parameterized
- The challenges of managing regression runs that must deal with many configurations
- Navigating the parameter permutation jungle: When a large design has numerous parameters, the possible combinations of parameters can become overwhelming. We will cover practical techniques for making sense of this “parameter explosion”, including a description of the useful pairwise approach.
- Other forms of configuration: Some RTL designs have quasi-static configuration that is not controlled by parameters or code generation, but is chosen at startup by pin-strap options or even by configuration registers that are normally set up just once immediately after a reset. Although this is not parameterization in the strict sense, and it has different effects on verification, many of the techniques in our workshop are applicable to this kind of configuration. We will briefly consider this, with particular emphasis on how it affects coverage.
Jeff Montesano is a Senior Consultant with Verilab specializing in constrained-random verification using SytemVerilog/UVM. He has participated in several award-winning papers over the years, including the DVCon USA best paper in 2018. In his free time, Jeff likes to play music in bands, cook, play hockey, and organize wine tasting events. Over the span of his 20-year career, he has worked throughout North America and Europe on projects ranging from networking equipment to military, consumer, and automotive electronics.
Dr. Paul Marriott is a veteran verification consultant with Verilab and specializes in high-reliability systems verification using SystemVerilog/UVM and specman/e. He has been a member of the DVCon Technical Program Committee for more than a decade and has authored many papers on verification topics. Over the span of his career, he has seen both the birth of Verilog and its adoption as a mature verification language. When not verifying today's complex chips, he participates in pyrotechnics and playing the piano (but not usually at the same time).
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