TUESDAY March 03, 3:00pm - 5:00pm | Fir
EVENT TYPE: REGULAR SESSION
Joanne DeGroat - Ohio State Univ.
Srinivasan Venkataramanan - VerifWorks Pvt. Ltd.
Tips and techniques that cover a wide range of verification topics.
|6.1||What Your Software Team Would Like the RTL Team to Know|
|We all want to have successful tape-outs. But the tape out isn’t the end of the story for any design project. There is a saying, “the chip doesn’t ship until the device driver works.” The design could be the most beautiful and functional in the world. The verification team could have verified every facet of the design. But if the software isn’t able to run, people at home won’t have their latest video game system or phone. And according to Harry Foster’s Verification Survey, specification issues are the second and third most common root cause of functional bugs.|
|Speaker:||Josh Rensch - Semifore, Inc.
|Author:||Josh Rensch - Semifore, Inc.
|6.2||It Should Just Work! Tips and Tricks for Creating Flexible, Vendor Agnostic Analog Behavioral Models|
|The advent of User Defined Nettypes (UDNs) in the SystemVerilog LRM has enabled analog behavioral model developers to move from tool-specific implementations of real number modeling to a vendor-agnostic approach. In addition, the UPF standard has been interpreted differently among the vendors in terms of the SV HDL interface. This paper offers guidance for developing flexible UDN and UPF aware behavioral models that will simulate in all major digital simulation tools.|
|Speaker:||Don Mills - Microchip Technology Inc.
|Author:||Chuck McClish - Microchip Technology Inc.
|6.3||Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification|
|The traditional SoC verification approach has until now been based on the fundamental assumption of known good processor IP from the mainstream semiconductor IP providers. With Open ISA’s such as RISC-V, developers can exploit a greater degree of implementation flexibility but must also assume a greater role in the verification task. To complement established techniques this paper illustrates the approach using an open-source random instruction generator for RISC-V with a cloud-based environment for capacity flexibility to compare implementation RTL against a reference simulation model. This latest framework covers the needs of specialist core designers and all SoC adopters.|
|Speaker:||Lee Moore - Imperas Software Ltd. & RISC-V International
|Authors:||Simon Davidmann - Imperas Software Ltd.
Lee Moore - Imperas Software Ltd. & RISC-V International
Richard Ho - Google, Inc.
Tao Liu - Google, Inc.
Doug Letcher - Metrics Technology, Inc.
Aimee Sutton - Metrics Technology, Inc.
|6.4||Multi-Level Replay of VIP Models in Isolation from Original Design Verification Environment to Enhance Protocol Analysis and Debug|
|The pressure of design complexity is growing as more functionality is condensed into systems This leads to higher complexity and resources for verification of the systems. While designs reuse IP blocks from third parties or reusable components from earlier versions of the designs, Verification environments are also getting complex and architected for reuse. Verification IPs play a critical role in making it happen. We propose the Replay based methodology to isolate Verification IP models with the relevant Activity Stimulus in a way that it caters to these challenges. The solution has been tested on several industry-standard protocols.|
|Speaker:||Akshay Sarup - Mentor, A Siemens Business
|Authors:||Umesh Mishra - Mentor Graphics (India) Pvt. Ltd.
Yamini Goyal - Mentor Graphics (India) Pvt. Ltd.
Amar S. Patel - Mentor, A Siemens Business & Mentor Graphics (India) Pvt. Ltd.
Yogesh Badaya - Mentor Graphics (India) Pvt. Ltd.