March 2-5, 2020

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY March 03, 3:00pm - 5:00pm | Monterey/Carmel
EVENT TYPE: REGULAR SESSION

SESSION 7
Power-Aware Design and Verification
Chair:
Amit Srivastava - Synopsys, Inc.
Co-Chair:
Progyna Khondkar - Mentor, A Siemens Business
Power-aware verification in a variety of applications.

7.1UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: The Big Q “Which is the Right Standard for My Design?”
To keep up with pace, the IEEE 1801 standard is continuously evolving to address low-power challenges of today’s complex designs. With the recent release of IEEE P1801-2018 (UPF 3.1), several new features have been added along with improving clarity on existing features. We have five UPF standards posing some questions about compatibility, differences, and challenges related to migration. For any low-power designer, the big question arises which is the right standard for my design. We will provide in-depth analysis and relevant examples of all new features introduced by UPF 3.1 along with highlighting any semantics differences with earlier versions.
 Speaker: Madhur Bhargava - Mentor, A Siemens Business
 Author: Madhur Bhargava - Mentor, A Siemens Business
7.2Low-Power Verification at Gate Level for Zen Microprocessor Core
In this paper, we present several low-power, gate-level checking techniques used at AMD on its Zen high-performance microprocessor core. Those techniques target respective low-power features that are either impossible, insufficient or difficult to be verified at RTL level only. Those targeted features verified at Gate level include scan shift reset, power gating and power on clock/reset. To prevent pilot errors as much as possible and improve execution/signoff efficiency, extensive automation has been put in place.
 Speakers: Keerthi Mullangi - Advanced Micro Devices, Inc.
Raluca Stan - Silicon Service SRL Romania
 Authors: Raluca Stan - Silicon Service SRL Romania
Diana Irimia - Silicon Service SRL Romania
Keerthi Mullangi - Advanced Micro Devices, Inc.
Baosheng Wang - Advanced Micro Devices, Inc.
7.3May the Powers be With You! – Unleashing Powerful New Features in UPF IEEE 1801
Low power requirements are omnipresent in modern-day electronic designs. IEEE 1801 (UPF) standard aids in this process. UPF provides necessary constructs to capture various power-related details at various levels of abstraction. As with any standard, UPF continues to expand, grow and add more capabilities. In this paper, authors share their experience in helping customers adopt some of the latest UPF features. Specifically, we will highlight the following features and how they benefit users: • bind_checker • SIMSTATE extensions • Information model in UPF Finally, we present a complete flow of building a custom rule checker for low power.
 Speaker: Srinivasan Venkataramanan - VerifWorks Pvt. Ltd. & VerifWorks, LLC
 Authors: Srinivasan Venkataramanan - VerifWorks Pvt. Ltd. & VerifWorks, LLC
Ajeetha Kumari - VerifWorks Pvt. Ltd. & CVC Pvt., Ltd.
Thejas KG - CVC Pvt., Ltd.
Vamsidhar D. Reddy - VerifWorks Pvt. Ltd.
7.4Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification
Although dynamic power usage has been a concern for decades, leakage power is a big concern for today’s SoC designs below 65nm. Reducing power consumption is essential to both mobile and data center applications, where lower power contributes to either longer battery life in IoT and handheld products while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic.
 Speaker: Ashish Amonkar - Cypress Semiconductor Corp.
 Authors: Ashish Amonkar - Cypress Semiconductor Corp.
Kurt Takara - Mentor, A Siemens Business
Avinash Agrawal - Mentor, A Siemens Business