DVCon U.S. 2016 Panel: Emulation + Static Verification Will Replace Simulation
Jim Hogan - Vista Ventures
Graham Bell - Real Intent, Inc.
Emulation and static verification have both been on a tear lately. With processor frequency at a plateau of few GHz and the “processor + system architecture + software” combine still catching up to the parallelism imperative, emulation has stepped up to fill the void nicely. Almost all chips go through some combination of emulation or FPGA-prototyping prior to product release. With a cloud-based pay-as-you-go model, emulation doesn’t even have to be expensive. Emulation is all about speed – the only way to push through stimuli through a high-end SOC.
Likewise static verification is also on a steep upward spiral with almost universal adoption of targeted tools for sign-off verification problems like CDC as well as increasing adoption for problems like power management, reset analysis, X-verification, timing exceptions, security, SOC integration etc. System-level functional formal verification has been on a slower but also positive adoption trajectory. On verification problems where they work well, static methods have come to deliver enhanced productivity and sign-off level confidence. Static tools ensure that design quality is already extremely high before simulation or emulation is started.
May be the verification paradigm of the future is to invest in high-end targeted static verification tools to get the design to a very high quality level, followed by very high-speed emulation or FPGA-prototyping for system-level functional verification. Where does that leave RTL simulation? Between a rock and a hard place! Gate-level simulation is already marginalized to doing basic sanity checks. May be RTL simulation will follow. Or will it?
Ashish Darbari - Imagination Technologies Ltd.
Richard Ho - Google, Inc.
Lauro Rizzatti - Consultant
Brian Hunter - Cavium, Inc.
Steven Holloway - Dialog Semiconductor
Pranav Ashar - Real Intent, Inc.