Aldec to unveil HES-7 High-speed AXI Transmission Channel at DVCon 2016
Sibridge Technologies Enhances Ethernet IP Cores with IEEE 1588 PTP
MEDIA ALERT : Flexras Technologies Showcases Automatic Hybrid RTL/Gate Partitioning at DVCON 2014
Agnisys announces ‘Mystic Tool’ at DVCon 2014
Agnisys announces DVCon specials for IDesignSpec™
DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 2
DVCon Panel Drill Down: “Where Does Design End and Verification Begin?” – Part 1
Imagination Technologies and Synopsys Collaborate to Enable Faster Emulation
Synopsys Delivers Industry’s Fastest Emulation System
Real Intent Presents at DVCon 2014
Truechip announces first customer shipment of USB 3.1 and UFS 2.0 VIP to early adoption partners
MEDIA ALERT: Breker Verification Systems to Demonstrate SoC Verification Software Portfolio at DVCon 2014 Verific Design Automation Adds Features to UPF Parser for Enhanced Support of IEEE Standard MEDIA ALERT: Verific to Demonstrate Enhancements to UPF Parser During DVCon MEDIA ALERT: Oski Technology to Highlight the Oski Formal Sign-Off Methodology at DVCon, Outlining Benefits of Applying Custom Abstraction Models During Formal Analysis MEDIA ALERT: OneSpin Solutions to Demonstrate New, Unique Observation Coverage Solution During DVCon OneSpin Solutions Introduces Unique, Formal-Based Observation Coverage Solution to Magnify Verification Closure PrecisionVerific Design Automation Adds Features to UPF Parser for Enhanced Support of IEEE Standard
Real Intent’s not-so-secret DVCon’13 Report
Dini Group now has Quad Virtex-7 FPGAs stackable to 112 M gates
IC Manage/Xilinx/CSR/Altera on IP-based design and verification
Calypto RTL Power Reduction and High Level Synthesis Report 2013
Breker Verification Systems Enhances TrekSoC GUI
Hitachi Information & Communication Engineering Selects Forte’s High-Level Synthesis Software
Atrenta to Present Assertion Synthesis Tutorial at DVCon 2013
Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013
Doulos announces upgrade to SystemVerilog portfolio
PRO DESIGN and ASICSoft To Exhibit Virtex 7 FPGA based Prototyping System at DVCon 2013
Atrenta to Present Assertion Synthesis Tutorial at DVCon 2013
Calypto Announces New President and CEO Sanjiv Kaul
Calypto’s Catapult Integrates with Real Intent’s Ascent Lint for Reliable RTL Implementation Flow
METHODICS UNVEILS INDSUTRY FIRST COMPLETE VERIFICATION MANAGEMENT SYSTEM FOR ANALOG DESIGN
