Industry Leaders Panel: Art or Science?

Industry Leaders Panel: Art or Science?

 

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Abstract:

The amount of time spent on verification has steadily risen such that it now consumes more time and resources than the design itself. The primary reason cited for this is that verification is a larger problem than design and can never be completed. At the same time, there are many aspects of the verification flow that are manual and these require significant knowledge and experience both of verification methodologies and the design. This has led to the perception that verification is an art and one which is difficult to master.

With the emergence of the Internet of Things, and in particular the embedded edge devices to support the IoT, many aspects of the design flow and its economics are changing, creating an opportunity to rethink the verification process. In addition, the maturing of formal methods is providing a richer tool suite than we have had in the past.

Is it possible to take some of the art out of verification, or to provide additional tools that would help engineers to master the art?

 

Panelists:

Janick Bergeron - Synopsys, Inc.
Harry Foster - Mentor Graphics Corp.
JL Gray - Cadence Design Systems, Inc.
Ken Knowlson - Intel Corp.
Bernard Murphy - Atrenta, Inc.