March 2-5, 2020

DoubleTree Hotel, San Jose, CA

Industry Leaders Panel: Did We Create the Verification Gap? - Part 3

Industry Leaders Panel: Did We Create the Verification Gap? - Part 3


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Part 3
Male #7: Hi, I'm (Raadish) from (inaudible) I see there's a lot of emphasis on improving the basic (inaudible) methodology from (sounds like:  RVM), (sounds like:  VMM), (sounds like:  AVM), OVM, UVM.  We are just trying to make it – creating a new buzzword and trying to make it more fancy.  But the system – or SoC verification, any ARM-based or CPU-based SoC verification that approach.  A solution for that, we are just going to – not trying to solve the problem and leaving it to the design houses, just collaborate more or (inaudible) or giving a little bit of (sounds like:  fuzzy) answers to those real problem.  So why there is no good effort in solving this SoC verification problem?
Mike Stellfox: First of all, I agree.  I think there's been a lot of focus, you know, and a lot of good has come with what's been done in UVM.  But, really, that was a methodology that's designed for IP, maybe subsystem, you know, exhaustive verification bottom-up.  And there hasn't been enough focus on the fact that if you look at today, most SoCs, most chips being designed, there's not a lot of new IPs.  You know, it's mostly integrating IPs from third parties internal highly configurable with a lot of software content.  And the flows today and the methods that are sort of best-known practices that we're – you see a lot of the papers and things here, really aren't about the SoC.  If you look at SoC, most companies I see it's kind of a wild west right now.  And I see there's a big opportunity, and that's actually a place where I'm focused to work with customers on developing SoC flows and optimizing those flows around integration of the IPs, highly configurable IPs, and being more software driven.  But I think we're kind of in the early days of that, but I think that's definitely the biggest area where the industry needs to focus to make improvements.
Male #2: Which I think the fact that we're having a standard at that level shows it's maturity.  And that's where the industry needs to focus now is the area where it's younger, more uncertain, is the SoC part, so – and software-driven verification.  So it's – it would be too early to do any standardization effort in that area because, frankly, we don't know exactly what works really well and what doesn't.  Good ideas, but…
Male #7: SoCs are not a new concept in last one or two years.  This has been there for at least 20 years that I've been seeing.  So I just feel that we are not paying enough attention to SoC verification solutions.
Male #2: Well, what has changed is their size.  Twenty years ago an entire SoC you could simulate on a 32-bit workstation without any problem.  And something like UVM would have been quite easy to carry.  Now it's very difficult.
Male #7: Even if it's a small SoC which is CPU-based with an ARM, UVM doesn't solve that problem.  That problem existed ten years back and it's still there today.
Bill Grundmann: I think what you're possibly confusing here is, one, is UVM and stuff like that are mechanisms for verification.  They don't do verification themselves.  Okay.  You still have to say, what are you trying to verify, and you have to wrap some kind of strategy around those tools and those mechanisms to actually cause a verification.  And right now, EDA doesn't know what you're doing specifically.  I mean, that's your secret sauce.  You're going to build something specifically to yourself, unless it's an ASSP that's being developed.  They may be involved in that.  But they are providing the mechanism, the common denominator to mechanisms, but you have to figure out what you're going to do with them.
Male #7: That's my exactly problem is they're only looking at the lowest IP (inaudible) verification.
Male: I disagree.
Bill Grundmann: I disagree.
Male #7: Okay.  So what solution do we have here for (inaudible)…
Male: There are solutions that are being developed is my point.  I – we're not ignoring the systems where it's at.  The system's where the challenge is at, the system's where the future is at.
Mike Stellfox: Right.  I mean, I can tell you at Cadence, we have a – there's a huge focus on that right now.  There's not a standard methodology like UVM.  And as Janick said, that's not where it is right now.  That doesn't make sense.  Right?  But there's definitely a pretty significant focus within Cadence, and I'm sure Synopsys and Mentor as well, on developing technology and flows and methodology I think about how to more effectively do that.  And I agree with you, that should be the number one focus area.  At least, you know, that's where most people are having the biggest gap, in my opinion.
Bill Grundmann: Well, I would add to that a little bit.  At the lowest level, a system on a chip, SoC, is a NAND gate.  Okay?  If what you've designed is a NAND gate, you can fully verify it with all kinds of mechanisms.  Okay?  But if a customer's expecting an OR gate, what's going to (sounds like:  find them)?  The problem is, you know, you have to say what it is you're trying to validate and what it is you're – what the expectation of the customer is.  And you could be having a perfect validation system of something that's irrelevant to what is expected in the marketplace.