In this panel, a few verification executives from leading EDA-IP and semiconductor/systems companies will discuss state of the art of their design verification environments that power the new generation of advanced processors and systems which could potentially change the semiconductor landscape. These include verifying IPs, System-on-Chips (SoCs), System-of-Chips and System-of-Systems for 5G-6G, Cloud and Edge Computing and AI-ML in emerging and growing verticals including Autonomous Vehicles, HealthTech, Mil-Aero, HPC and more.
Some of this discussion will center around the reality behind AI-ML algorithms to transform verification/validation and system-level testing of such systems. Are we there yet? What will it take to make these systems really work for us? Is AI-ML sufficient? What kind of standards will we need to make it all work?
Here are some among many open challenges that we would like our panelists to address:
- What does it take to verify chips, SoCs and systems for 5G-6G, Edge computing and AI-ML?
- UVM, ISO26262, DO-254, Python: what next? How best can we verify software-driven hardware, system-of-systems? What kind of standards would we need beyond these?
- How do we verify with emerging metrics beyond functionality? How do we deal with increasing complexity?
- Functional safety, security, Performance per watts, SLM
- At what step do AI-ML algorithms help in pre- and post-silicon verification?
- Will they replace or complement formal approaches?
- Can they help us in scaling with heterogeneous architectures using chiplets to create System-of-Chips and System-of-Systems?
- Are there any limitations to the use of AI-ML algorithms?
- What will it take to get to our longer-term vision of predictable RTL and Gate-level signoff, and first-pass Silicon?
Shankar Hemmady, Founder and CEO, Blue Horizons
Prith Banerjee, CTO, Ansys
William Hung, Vice President of Engineering, Cadence
Saad Godil, Director of Applied Deep Learning Research, Nvidia
Manish Pandey, Fellow & VP R&D, Synopsys
Jean-Marie Brunet, VP and GM of Hardware-Assisted Verification, Siemens