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  • Home
  • About
    • Steering Committee
    • Technical Program Committee
    • History & Archive
    • DVCon U.S. Conference Sponsor & Privacy Policy
  • Author / Speaker Information
    • Abstract Submissions
    • Tutorial/Workshop Submissions
    • Panel Submissions
    • Speaker Resources and Guidelines
    • Pre-Recorded Video Instructions
  • Sponsors & Exhibitors
    • Sponsor & Exhibitor Resources
    • 2023 Sponsors
    • 2023 Exhibitors
  • Program
    • 2023 Program Grid
    • Keynote: Dirk Didascalou
    • Panel: Systems are Evolving. Is Verification Keeping Up?
    • Panel: AI-ML Algorithms are Transforming Verification: Separating Hype from Reality
    • 2023 Accepted Papers
    • 2022 Program Information
      • Welcome Message from the General Chair
      • Program Grid
      • Keynote: Manish Pandey
      • Stuart Sutherland Best Paper & Best Poster Award Recipients
      • 2022 Sponsors & Exhibitors
      • Virtual Exhibit Hall (Gather.Town)
  • Registration
  • Hotel & Travel
  • Media
    • News
      • Press Release – December 8, 2022
      • Press Release – June 8, 2022
      • Press Release – May 24, 2022
      • Press Release – March 8, 2022
      • Breakfast Bytes – February 22, 2022
      • Press Release – February 22, 2022
      • EDA Café: 2022 General Chair Interview
      • SemiWiki: 2022 Gather.Town and Accellera Coverage
      • EE Journal Fish Fry – February 11, 2022
      • Press Release – February 8, 2022
      • Press Release – December 8, 2021
      • Press Release – October 12, 2021
      • Press Release – July 28, 2021
      • Press Release – July 12, 2021
    • Videos
    • Photos
      • DVCon US 2018 Photos
      • DVCon US 2017 Photos

Presenter Type: Oral/Lecture

Modeling Memory Coherency during concurrent/simultaneous accesses

Subramoni Parameswaran, Xilinx

Advanced UVM command line processor for central maintenance and randomization of control knobs

Siddharth Krishna Kumar, Samsung Austin Research Center

Optimizing Turnaround Times In Continuous Integration Using Scheduler Implementation

Robert Strong, Samsung

What Does the Sequence Say? Powering Productivity with Polymorphism

Rich Edelman, Siemens EDA

Path-based UPF Strategies Optimally Manage Power on your Designs

Progyna Khondkar, Siemens EDA

Co-Developing IP and SoC Bring-up Firmware with PSS

Matthew Ballance, Siemens Digital Industries Software

Metadata Based Testbench Generation

Daeseo Cha, Samsung Electronics

A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example

Charles Dancak, Betasoft Consulting Inc

Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?

Brandon Skaggs, Cypress Semiconductor, An Infineon Technologies Company

Caching Tool Run Results in Large-Scale RTL Development Projects

Ashfaq Khan, Intel Corporation

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